--- title: "Ripple counter; mod-10 ripple counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:mod10-ripple-counter" source: https://www.bctengineer.com/q/semester_3/digital_logic/mod10-ripple-counter site: BCT Engineering --- # Ripple counter; mod-10 ripple counter Digital Logic · Chapter 8: Counters - Asked in: 2068 Chaitra, 1+7 marks - Video: [Decade (BCD) Ripple Counter](https://www.youtube.com/watch?v=fKVZpupyP_o) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod10-ripple-counter - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Define ripple counter. Explain the operation of mod-10 ripple counter with timing diagram. ## Short answer A ripple counter has flip-flops clocked by previous stage outputs, causing propagation delay. A mod-10 ripple counter uses four JK flip-flops in toggle mode. After count 9 (1001), the next pulse gives 1010 momentarily; a NAND gate on Q3 and Q1 resets all FFs to 0000, providing a divide-by-10 output. ## Answer #### Ripple counter A **ripple counter** (asynchronous counter) is a counter in which only the first flip-flop receives the external clock, and the output of each flip-flop acts as the clock of the next one. The change of state ripples through the stages one after another. #### Mod-10 ripple counter **Construction** - 10 states (0–9) need 4 flip-flops, since $2^3 < 10 \le 2^4$. - Four negative-edge JK flip-flops with $J = K = 1$ (toggle mode). CLK → FF0, $Q_0$ → FF1, $Q_1$ → FF2, $Q_2$ → FF3. - At count 10 (**1010**), $Q_3$ and $Q_1$ are both 1 for the first time. A NAND gate of $Q_3$ and $Q_1$ drives the active-low CLEAR of all flip-flops, so the counter returns to 0000. ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | | NAND |o--> CLR of all FFs (active low) Q1 ---| | ``` **Operation** 1. Clear all flip-flops: 0000. 2. Each falling edge of CLK toggles FF0. FF1 toggles every time $Q_0$ falls 1→0; FF2 every time $Q_1$ falls; FF3 every time $Q_2$ falls. The outputs therefore count up in binary. 3. After the 9th pulse the count is 1001. The 10th pulse makes $Q_0$ fall, which toggles $Q_1$ to 1, giving 1010 for a moment. The NAND output becomes 0 and clears all flip-flops to 0000. The next cycle begins. | Pulse | Q3 Q2 Q1 Q0 | Count | |---|---|---| | 0 | 0000 | 0 | | 1 | 0001 | 1 | | 2 | 0010 | 2 | | 3 | 0011 | 3 | | 4 | 0100 | 4 | | 5 | 0101 | 5 | | 6 | 0110 | 6 | | 7 | 0111 | 7 | | 8 | 1000 | 8 | | 9 | 1001 | 9 | | 10 | 1010 → 0000 | 0 | **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 8 9 0 ``` - $Q_0$ changes at every falling clock edge ($f/2$). - $Q_1$, $Q_2$, $Q_3$ change at the falling edges of $Q_0$, $Q_1$, $Q_2$. - $Q_3$ is high during counts 8 and 9 and gives $f_{clk}/10$. - In the real circuit each stage adds one propagation delay and a narrow spike appears on $Q_1$ at the 10th pulse (state 1010 before reset). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is a ripple counter? A. All flip-flops get the same clock B. Only the first flip-flop gets the external clock; each output clocks the next C. It has a parallel load D. It uses only D flip-flops Answer: B. The change of state ripples through the stages one after another. (Key point: Ripple counter definition) 2. Why are 4 flip-flops needed for mod-10? A. 2^3 = 8 < 10 <= 2^4 = 16 B. 10 states need 10 flip-flops C. 2^2 = 4 is enough D. JK flip-flops count two bits each Answer: A. 3 flip-flops give only 8 states, so 4 are needed. (Key point: Number of flip-flops) 3. What triggers the clear in the mod-10 ripple counter? A. NAND of Q3 and Q1 at 1010 drives active-low CLEAR B. NAND of Q3 and Q0 at 1001 C. AND of Q2 and Q1 at 0110 D. The external clock Answer: A. 1010 is the first state with Q3 = Q1 = 1; NAND going low clears all flip-flops. (Key point: Reset decoding) 4. What appears on Q1 at the 10th pulse in the real circuit? A. A permanent high level B. A narrow spike before the reset C. Nothing D. A doubled frequency Answer: B. State 1010 appears briefly before clearing, causing a narrow spike on Q1. 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