--- title: "Mod-10 negative edge ripple counter with JK" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:mod10-ripple-jk-negative-edge" source: https://www.bctengineer.com/q/semester_3/digital_logic/mod10-ripple-jk-negative-edge site: BCT Engineering --- # Mod-10 negative edge ripple counter with JK Digital Logic · Chapter 8: Counters - Asked in: 2081 Bhadra, 2+6 marks - Video: [mod 10 asynchronous counter](https://www.youtube.com/watch?v=k7dL2Sbr7Z4) — Justin John - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod10-ripple-jk-negative-edge - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Define a sequential logic circuit. Explain the mod-10 negative edge-triggered ripple counter with its timing diagram. Use JK flip-flops in your design. ## Short answer A sequential logic circuit output depends on present inputs and stored state (past history), requiring memory elements. A mod-10 negative-edge ripple counter uses 4 JK flip-flops in toggle mode (J=K=1), cascaded with Q outputs clocking next FFs, counting 0000–1001. It resets to 0000 on the 10th pulse via a NAND gate on Q3 and Q1 driving clear. ## Answer #### Sequential logic circuit A **sequential logic circuit** is a circuit whose output depends on the present inputs **and** on the past history (stored state) of the circuit. It contains memory elements (flip-flops or latches) and a feedback path; flip-flops, registers and counters are examples. #### Mod-10 negative-edge ripple counter A mod-10 (decade) ripple counter has 10 states, 0000 to 1001. Since $2^3 < 10 \le 2^4$, four JK flip-flops are used. **Connections** - All J and K inputs are tied to logic 1, so every flip-flop toggles on its active (falling) clock edge. - The external clock goes to FF0 only. $Q_0$ is the clock of FF1, $Q_1$ of FF2 and $Q_2$ of FF3 (negative-edge triggering means a stage toggles when the previous Q falls from 1 to 0, which gives up counting). - Count 10 = 1010 must not be held. It is the first state with $Q_3 = Q_1 = 1$, so $\overline{Q_3Q_1}$ (NAND) is fed to the active-low CLEAR of all flip-flops. ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | | NAND |o--> CLR of all FFs (active low) Q1 ---| | ``` **Operation** 1. Initially all flip-flops are cleared: $Q_3Q_2Q_1Q_0 = 0000$. 2. Every falling clock edge toggles FF0. Whenever $Q_0$ goes 1→0, FF1 toggles; whenever $Q_1$ goes 1→0, FF2 toggles; whenever $Q_2$ goes 1→0, FF3 toggles. The count rises 0, 1, 2, …, 9. 3. On the 10th falling edge the outputs try to become 1010. At once the NAND output goes low and clears all flip-flops, so the counter returns to 0000. The false state 1010 exists only for a few nanoseconds. | Clock pulse | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | |---|---|---|---|---|---|---|---|---|---|---|---| | Q3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | | Q2 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | Q1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | | Q0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 8 9 0 ``` Each output changes on the falling edge of the signal that clocks it. $Q_3$ is high only for counts 8 and 9, and its frequency is $f_{clk}/10$. In a real circuit each stage adds a propagation delay $t_{pd}$, so the outputs ripple and a narrow spike appears on $Q_1$ at the reset. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What defines a sequential logic circuit? A. Its output depends only on present inputs B. Its output depends on present inputs and on stored past state C. It contains only gates with no feedback D. It has no clock Answer: B. A sequential circuit has memory elements and feedback, so output depends on present inputs and past history. (Key point: Sequential circuit definition) 2. How are the JK flip-flops connected in the mod-10 negative-edge ripple counter? A. J = K = 0; all clocked by CLK B. J = K = 1; CLK to FF0 only and Q0, Q1, Q2 clock the next stages C. J = Q', K = Q; CLK to every stage D. J = K = 1; Q0' clocks FF1 Answer: B. J = K = 1 makes each stage toggle, and with negative-edge triggering using Q as the next clock gives an up count. (Key point: J, K and clock connections) 3. What clears the counter at the 10th pulse? A. NAND of Q3 and Q1 (state 1010) to the active-low CLEAR of all flip-flops B. NAND of Q3 and Q0 (state 1001) C. AND of Q2 and Q1 to the clock D. A manual reset switch Answer: A. 1010 is the first state with Q3 = Q1 = 1; NAND of these clears all flip-flops to 0000. (Key point: Reset logic) 4. What is true about state 1010 and the Q3 frequency? A. 1010 is held for a full clock; Q3 is f_clk/5 B. 1010 exists only a few ns, causing a spike on Q1; Q3 is f_clk/10 C. 1010 never occurs; Q3 is f_clk/16 D. 1010 is held; Q3 is f_clk/10 Answer: B. The false state lasts only for the clear delay, giving a narrow spike on Q1, and the counter divides the clock by 10. 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