--- title: "Sync vs async; MOD-10 synchronous counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:mod10-synchronous-counter" source: https://www.bctengineer.com/q/semester_3/digital_logic/mod10-synchronous-counter site: BCT Engineering --- # Sync vs async; MOD-10 synchronous counter Digital Logic · Chapter 8: Counters - Asked in: 2079 Baisakh, 2+6 marks - Video: [MOD 10 Synchronous counter using T flip flop| Design Mod-10 synchronous Up counter using T flip flop](https://www.youtube.com/watch?v=y1vyURDKYNY) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod10-synchronous-counter - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Define Synchronous and Asynchronous counter. Design a MOD-10 synchronous counter and draw its timing diagram. ## Short answer Synchronous counters have all flip-flops clocked together; asynchronous counters ripple clock from previous stage. MOD-10 synchronous counter uses 4 JK flip-flops: J3=Q2Q1Q0, K3=Q0; J2=K2=Q1Q0; J1=Q3'Q0, K1=Q0; J0=K0=1, counting 0-9 then return to 0. ## Answer #### Definitions - **Synchronous counter:** a counter in which all flip-flops are driven by the same clock pulse, so all outputs change at the same time. Logic gates decide which flip-flops toggle. - **Asynchronous (ripple) counter:** a counter in which only the first flip-flop gets the external clock; each later flip-flop is clocked by the output of the previous one, so the outputs change one after another. #### Design of MOD-10 synchronous counter (JK flip-flops) **Step 1:** 10 states (0000–1001) need 4 JK flip-flops ($Q_3Q_2Q_1Q_0$). States 1010–1111 are don't cares. **Step 2: Excitation table** (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0) | Present Q3Q2Q1Q0 | Next Q3Q2Q1Q0 | J3 | K3 | J2 | K2 | J1 | K1 | J0 | K0 | |---|---|---|---|---|---|---|---|---|---| | 0000 | 0001 | 0 | X | 0 | X | 0 | X | 1 | X | | 0001 | 0010 | 0 | X | 0 | X | 1 | X | X | 1 | | 0010 | 0011 | 0 | X | 0 | X | X | 0 | 1 | X | | 0011 | 0100 | 0 | X | 1 | X | X | 1 | X | 1 | | 0100 | 0101 | 0 | X | X | 0 | 0 | X | 1 | X | | 0101 | 0110 | 0 | X | X | 0 | 1 | X | X | 1 | | 0110 | 0111 | 0 | X | X | 0 | X | 0 | 1 | X | | 0111 | 1000 | 1 | X | X | 1 | X | 1 | X | 1 | | 1000 | 1001 | X | 0 | 0 | X | 0 | X | 1 | X | | 1001 | 0000 | X | 1 | 0 | X | 0 | X | X | 1 | **Step 3: K-maps** (only the non-trivial ones) | J1: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 00 | 0 | 1 | X | X | | 01 | 0 | 1 | X | X | | 11 | X | X | X | X | | 10 | 0 | 0 | X | X | | J3: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 00 | 0 | 0 | 0 | 0 | | 01 | 0 | 0 | 1 | 0 | | 11 | X | X | X | X | | 10 | X | X | X | X | | K3: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 00 | X | X | X | X | | 01 | X | X | X | X | | 11 | X | X | X | X | | 10 | 0 | 1 | X | X | $K_1 = Q_0$ and $J_2 = K_2 = Q_1Q_0$ are read the same way. **Step 4: Equations** $$ \begin{aligned} &J_3 = Q_2Q_1Q_0,\quad K_3 = Q_0 \\ &J_2 = Q_1Q_0,\quad K_2 = Q_1Q_0 \\ &J_1 = \overline{Q_3}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned} $$ **Step 5: Circuit diagram** ```text +-----+ +-----+ +-----+ +-----+ J0>|J Q|-Q0 J1>|J Q|-Q1 J2>|J Q|-Q2 J3>|J Q|-Q3 | FF0 | | FF1 | | FF2 | | FF3 | K0>|K | K1>|K | K2>|K | K3>|K | +--o--+ +--o--+ +--o--+ +--o--+ | | | | CLK---+-------------+-------------+-------------+ J0 = K0 = 1 J1 = Q3'.Q0 K1 = Q0 J2 = K2 = Q1.Q0 J3 = Q2.Q1.Q0 K3 = Q0 ``` **Step 6: Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾|_______ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾ Cnt 0 1 2 3 4 5 6 7 8 9 0 1 ``` All flip-flops change together on the falling clock edge. $Q_3$ is high for counts 8 and 9, giving $f_{Q_3} = f_{clk}/10$. The unused states return to the main count within two clocks (1010→1011→0100, 1100→1101→0100, 1110→1111→0000), so the counter is self-starting. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What distinguishes a synchronous counter from an asynchronous (ripple) counter? A. Every flip-flop gets the same clock pulse, so all outputs change together B. Only the first flip-flop gets the clock and the rest are clocked by the previous output C. It uses T flip-flops only while a ripple counter uses JK only D. It needs no gates between flip-flops Answer: A. In a synchronous counter all flip-flops share one clock and gates decide which toggle; in a ripple counter later stages are clocked by earlier outputs. (Key point: Synchronous vs asynchronous) 2. Why does the MOD-10 counter need 4 flip-flops, and what happens to states 1010-1111? A. 3 flip-flops give 8 states, so 4 are needed; the 6 unused states are don't cares B. 10 states need 10 flip-flops; the rest are unused C. 4 flip-flops are needed because JK has 4 inputs; unused states are forced to 0 D. 2^3 = 8 is enough; states 1010-1111 are counted too Answer: A. 2^3 = 8 < 10 <= 2^4, so 4 flip-flops are used. The six unused states are marked don't care in the K-maps. (Key point: Number of flip-flops) 3. For a JK flip-flop going from 1 to 0, which J and K inputs are required? A. J = 0, K = X B. J = X, K = 1 C. J = 1, K = X D. J = X, K = 0 Answer: B. For the 1 to 0 transition J is a don't care and K must be 1 (reset or toggle). (Key point: JK excitation values) 4. Which equations come from the K-maps for the MOD-10 synchronous counter? A. J3 = Q2Q1Q0, K3 = Q0, J1 = Q3'Q0, K1 = Q0 B. J3 = Q3Q0, K3 = Q2Q1Q0, J1 = Q0, K1 = Q3'Q0 C. J3 = Q0, K3 = Q2Q1Q0, J1 = Q3Q0, K1 = 1 D. J3 = 1, K3 = 1, J1 = Q0, K1 = Q0 Answer: A. Q3 sets at 7 to 8 (Q2Q1Q0 = 1) and resets at 9 to 0 (K3 = Q0); Q1 is blocked at 9 by Q3', so J1 = Q3'Q0. (Key point: MOD-10 equations) ## Close variants set in other exams - [Counter; MOD-6 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acounter-mod6-synchronous) — Digital Logic, chapter 8, asked 3× ## Related in Digital Logic - [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3× - [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8 - [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8 - [Sync vs async; 3-bit synchronous up counter (T)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-up-counter-3bit-t) — Digital Logic, chapter 8 - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× - [Comb vs seq; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-comb-seq) — Digital Logic, chapter 8, asked 3× ## Related in other subjects - [Synchronous/asynchronous bus; LXI timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-bus-lxi-timing) — Microprocessor, chapter 2, asked 2× - [Transmission channels; sync vs async](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Atransmission-modes) — Data Communication, chapter 1 - [Multiplexing; synchronous vs asynchronous TDM](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Amux-compare-sync-async-tdm) — Data Communication, chapter 6, asked 6×