--- title: "Sync vs async; mod-12 synchronous counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:mod12-synchronous-counter" source: https://www.bctengineer.com/q/semester_3/digital_logic/mod12-synchronous-counter site: BCT Engineering --- # Sync vs async; mod-12 synchronous counter Digital Logic · Chapter 8: Counters - Asked in: 2070 Chaitra, 2+6 marks - Video: [Synchronous Counter Design](https://www.youtube.com/watch?v=w2qP_Vt51yk) — TutorialsPoint - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod12-synchronous-counter - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Differentiate synchronous and asynchronous sequential circuits. Explain the operation of mod-12 synchronous counter with timing diagram. ## Short answer Synchronous circuits use a common clock; asynchronous change with inputs. A mod-12 synchronous counter uses four JK flip-flops. J0=K0=1, J1=K1=Q0, J2=Q3'Q1Q0, K2=Q1Q0, J3=Q2Q1Q0, K3=Q1Q0. It counts 0-11 then resets. The timing diagram shows Q0 toggling each clock, with Q3 high for counts 8-11. ## Answer #### Synchronous vs asynchronous sequential circuits | Point | Synchronous | Asynchronous | |---|---|---| | Timing | State changes only at clock edges | State changes whenever inputs change | | Clock | Common clock to all flip-flops | No common clock | | Memory elements | Clocked flip-flops | Unclocked latches or gate delays (or FFs clocked by other FFs) | | Speed | Limited by clock frequency | Can be faster | | Problems | Clock skew | Races, hazards, false states | | Design | Easier, systematic | Harder | | Example | Synchronous counter | Ripple counter | #### Mod-12 synchronous counter It counts 0000 to 1011 (0–11) and returns to 0000. Four JK flip-flops share a common clock; states 1100–1111 are don't cares. **Excitation table** | Present Q3Q2Q1Q0 | Next Q3Q2Q1Q0 | J3 | K3 | J2 | K2 | J1 | K1 | J0 | K0 | |---|---|---|---|---|---|---|---|---|---| | 0000 | 0001 | 0 | X | 0 | X | 0 | X | 1 | X | | 0001 | 0010 | 0 | X | 0 | X | 1 | X | X | 1 | | 0010 | 0011 | 0 | X | 0 | X | X | 0 | 1 | X | | 0011 | 0100 | 0 | X | 1 | X | X | 1 | X | 1 | | 0100 | 0101 | 0 | X | X | 0 | 0 | X | 1 | X | | 0101 | 0110 | 0 | X | X | 0 | 1 | X | X | 1 | | 0110 | 0111 | 0 | X | X | 0 | X | 0 | 1 | X | | 0111 | 1000 | 1 | X | X | 1 | X | 1 | X | 1 | | 1000 | 1001 | X | 0 | 0 | X | 0 | X | 1 | X | | 1001 | 1010 | X | 0 | 0 | X | 1 | X | X | 1 | | 1010 | 1011 | X | 0 | 0 | X | X | 0 | 1 | X | | 1011 | 0000 | X | 1 | 0 | X | X | 1 | X | 1 | **Equations (from K-maps)** $$ \begin{aligned} &J_3 = Q_2Q_1Q_0,\quad K_3 = Q_1Q_0 \\ &J_2 = \overline{Q_3}Q_1Q_0,\quad K_2 = Q_1Q_0 \\ &J_1 = Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned} $$ **Circuit diagram** ```text +-----+ +-----+ +-----+ +-----+ J0>|J Q|-Q0 J1>|J Q|-Q1 J2>|J Q|-Q2 J3>|J Q|-Q3 | FF0 | | FF1 | | FF2 | | FF3 | K0>|K | K1>|K | K2>|K | K3>|K | +--o--+ +--o--+ +--o--+ +--o--+ | | | | CLK---+-------------+-------------+-------------+ J0 = K0 = 1 J1 = K1 = Q0 J2 = Q3'.Q1.Q0 K2 = Q1.Q0 J3 = Q2.Q1.Q0 K3 = Q1.Q0 ``` **Operation** - $Q_0$ toggles on every clock edge. - $Q_1$ toggles whenever $Q_0 = 1$. - $Q_2$ sets when $Q_1Q_0 = 1$ and $Q_3 = 0$ (at 3 → 4), and resets when $Q_1Q_0 = 1$ (at 7 → 8). At 11 (1011), $Q_3 = 1$ blocks $J_2$, so $Q_2$ stays 0. - $Q_3$ sets at 7 → 8 ($Q_2Q_1Q_0 = 1$) and resets at 11 → 0 ($Q_1Q_0 = 1$ with $Q_3 = 1$). - So at the 12th clock, 1011 goes directly to 0000 with no false intermediate state. **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 8 9 10 11 0 ``` $Q_3$ is high for counts 8–11, giving $f_{clk}/12$. Unused states go 1100 → 1101 → 1110 → 1111 → 0000, so the counter is self-starting. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which statement correctly contrasts synchronous and asynchronous sequential circuits? A. Synchronous change state only at clock edges; asynchronous change whenever inputs change B. Asynchronous use a common clock; synchronous do not C. Synchronous have races and hazards; asynchronous do not D. Synchronous have no memory Answer: A. Synchronous circuits use a common clock and are easier to design; asynchronous ones are prone to races and hazards. (Key point: Sync vs async sequential) 2. What are J3 and K3 for the mod-12 synchronous counter? A. J3 = Q2Q1Q0, K3 = Q1Q0 B. J3 = Q1Q0, K3 = Q2Q1Q0 C. J3 = Q3'Q1Q0, K3 = Q1Q0 D. J3 = K3 = Q0 Answer: A. Q3 sets at 7 to 8 (Q2Q1Q0 = 1) and resets at 11 to 0 (Q1Q0 = 1 while Q3 = 1). (Key point: Equations for Q3) 3. Why does J2 include Q3'? A. To block Q2 from setting at 11 so the count goes to 0000 B. To make Q2 toggle at every clock C. To set Q2 at 7 to 8 D. To avoid using K2 Answer: A. At 1011 Q3 = 1 makes J2 = 0, so Q2 stays 0 and 1011 goes directly to 0000. (Key point: Role of Q3' in J2) 4. What happens at the 12th clock? A. 1011 goes directly to 0000 with no false intermediate state B. 1011 goes to 1100 then clears C. 1011 goes to 1111 D. The counter stops Answer: A. All flip-flops change together, so there is no transient state, unlike a ripple counter. (Key point: Direct transition) 5. What is the frequency of Q3? A. f_clk/8 B. f_clk/12 C. f_clk/16 D. f_clk/4 Answer: B. Q3 is high for counts 8-11, one cycle per 12 clocks. (Key point: Frequency) ## Close variants set in other exams - [Comb vs seq; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-comb-seq) — Digital Logic, chapter 8, asked 3× - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× ## Related in Digital Logic - [Sync vs async; MOD-10 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-synchronous-counter) — Digital Logic, chapter 8, asked 2× - [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8 - [Synchronous circuits; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-counter-define) — Digital Logic, chapter 8, asked 2× - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8 - [Sync vs async; 3-bit synchronous up counter (T)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-up-counter-3bit-t) — Digital Logic, chapter 8 ## Related in other subjects - [Synchronous/asynchronous bus; LXI timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-bus-lxi-timing) — Microprocessor, chapter 2, asked 2× - [Transmission channels; sync vs async](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Atransmission-modes) — Data Communication, chapter 1 - [Synchronous vs asynchronous serial transmission](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-serial) — Microprocessor, chapter 4, asked 3×