---
title: "Mod-5 Gray code synchronous up counter"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:mod5-gray-sync-counter"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mod5-gray-sync-counter
site: BCT Engineering
---

# Mod-5 Gray code synchronous up counter

Digital Logic · Chapter 8: Counters

- Asked in: 2080 Baisakh, 8 marks
- Video: [172 Design of Synchronous MOD   6 Gray Counter](https://www.youtube.com/watch?v=2857t9pHtT8) — SP Engg. ACADEMY
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod5-gray-sync-counter
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Design mod-5 Gray code synchronous up-counter with negative edge triggering clock system. (Use JK flip-flops).

## Short answer

A mod-5 Gray code synchronous up-counter uses three JK flip-flops on negative edge. Sequence: 000, 001, 011, 010, 110, 000. Flip-flop equations: J2 = Q1 Q0', K2 = 1; J1 = Q0, K1 = Q2; J0 = Q1', K0 = Q1. Counter is self-starting.

## Answer

A **mod-5 Gray code counter** steps through the first five codes of the 3-bit Gray sequence, changing only one bit per clock:
$$
000 \to 001 \to 011 \to 010 \to 110 \to 000
$$

#### Step 1: Flip-flops and unused states
- 5 states need $n = 3$ JK flip-flops ($Q_2Q_1Q_0$), all clocked together on the **negative (falling) edge**.
- Unused states 100, 101 and 111 are treated as don't cares (X).

#### Step 2: Excitation table
JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

| Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 011 | 0 | X | 1 | X | X | 0 |
| 011 | 010 | 0 | X | X | 0 | X | 1 |
| 010 | 110 | 1 | X | X | 0 | 0 | X |
| 110 | 000 | X | 1 | X | 1 | 0 | X |

#### Step 3: K-maps
| J0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | X | X | 0 |
| 1 | X | X | X | 0 |

| K0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | 0 | 1 | X |
| 1 | X | X | X | X |

| J1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | X | X |
| 1 | X | X | X | X |

| K1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 0 | 0 |
| 1 | X | X | X | 1 |

| J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | X | X | X | X |

$K_2$: Q2 = 1 only in state 110, where it must reset, and the other cells are X, so $K_2 = 1$.

#### Step 4: Equations
$$
\begin{aligned} &J_2 = Q_1\overline{Q_0},\quad K_2 = 1 \\ &J_1 = Q_0,\quad K_1 = Q_2 \\ &J_0 = \overline{Q_1},\quad K_0 = Q_1 \end{aligned}
$$

#### Step 5: Circuit diagram
```text
   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = Q1'    K0 = Q1
J1 = Q0     K1 = Q2
J2 = Q1.Q0' K2 = 1
```
Only one 2-input AND gate is needed, because $\overline{Q_1}$ and $\overline{Q_0}$ can be taken directly from the flip-flops' $\overline{Q}$ outputs.

#### Step 6: Check of unused states
| Unused state | Next state |
|---|---|
| 100 | 001 |
| 101 | 011 |
| 111 | 000 |

All unused states enter the main sequence after one clock, so the counter is **self-starting**.

#### Step 7: Timing diagram (negative edge)
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾|_______|‾‾‾
Q0   ____|‾‾‾‾‾‾‾|___________|‾‾‾‾‾‾‾
Cnt  000  001 011 010 110 000 001 011
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the mod-5 Gray code count sequence?
   A. 000, 001, 010, 011, 100
   B. 000, 001, 011, 010, 110, then 000
   C. 000, 001, 011, 111, 101
   D. 000, 100, 110, 010, 011
   Answer: B. The first five 3-bit Gray codes are 000, 001, 011, 010, 110, and then it returns to 000. (Key point: Gray sequence)

2. Which states are don't cares?
   A. 000, 001 and 011
   B. 100, 101 and 111
   C. 010 and 110
   D. There are none
   Answer: B. Five of eight states are used; 100, 101 and 111 never occur and are don't cares. (Key point: Unused states)

3. Which equations are correct?
   A. J2 = Q1 Q0', K2 = 1; J1 = Q0, K1 = Q2; J0 = Q1', K0 = Q1
   B. J2 = Q1, K2 = 0; J1 = Q0', K1 = Q2'; J0 = Q1, K0 = Q1'
   C. J2 = K2 = 1; J1 = K1 = Q0; J0 = K0 = Q1
   D. J2 = Q0, K2 = Q1; J1 = Q2, K1 = Q0; J0 = 1, K0 = 1
   Answer: A. The K-maps give J2 = Q1Q0', K2 = 1, J1 = Q0, K1 = Q2, J0 = Q1' and K0 = Q1. (Key point: Simplified equations)

4. What does the unused state 100 go to on the next clock?
   A. 001
   B. 100
   C. 011
   D. 000
   Answer: A. From 100: J0 = Q1' = 1 sets Q0, K1 = Q2 = 1 keeps Q1 at 0, K2 = 1 clears Q2, giving 001, which is in the main sequence. (Key point: Self-starting)

## Related in Digital Logic

- [MOD-6 synchronous counter, negative edge JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-negative-edge) — Digital Logic, chapter 8, asked 4×
- [Mod-10 negative edge ripple counter with JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-ripple-jk-negative-edge) — Digital Logic, chapter 8
- [SR equation; mod-5 counter using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-equation-mod5-d-counter) — Digital Logic, chapter 8
- [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8
- [Mod-5 synchronous counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-synchronous-jk) — Digital Logic, chapter 8, asked 4×
- [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8
