---
title: "Synchronous MOD-5 counter; counter applications"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:mod5-sync-applications"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mod5-sync-applications
site: BCT Engineering
---

# Synchronous MOD-5 counter; counter applications

Digital Logic · Chapter 8: Counters

- Asked in: 2073 Shrawan, 6 marks
- Video: [MOD -5 SYNCHRONOUS COUNTER USING T FLIP FLOP](https://www.youtube.com/watch?v=OnR5PFk-EQE) — Tech Boom Tech
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod5-sync-applications
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Design a synchronous MOD-5 counter along with block diagram and timing diagrams. Also write the applications of counters and shift registers.

## Short answer

A synchronous MOD-5 counter uses three JK flip-flops with J0=Q2', K0=1; J1=K1=Q0; J2=Q1Q0, K2=1. It counts 0-4. Applications include frequency division, digital clocks, event counting, ADCs, and program counters. Shift registers are used for data conversion, storage, ring counters, and CRC.

## Answer

#### Synchronous MOD-5 counter
A MOD-5 counter has 5 states, 000 → 001 → 010 → 011 → 100 → 000. Three JK flip-flops ($2^3 = 8 \ge 5$) share a common clock. States 101, 110, 111 are don't cares.

**Excitation table** (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

| Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 010 | 0 | X | 1 | X | X | 1 |
| 010 | 011 | 0 | X | X | 0 | 1 | X |
| 011 | 100 | 1 | X | X | 1 | X | 1 |
| 100 | 000 | X | 1 | 0 | X | 0 | X |

**K-maps**

| J0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | X | X | 1 |
| 1 | 0 | X | X | X |

| J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | X | X | X | X |

The other maps give $K_0 = 1$, $J_1 = K_1 = Q_0$ and $K_2 = 1$.

**Equations**
$$
\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = 1 \\ &J_1 = Q_0,\quad K_1 = Q_0 \\ &J_0 = \overline{Q_2},\quad K_0 = 1 \end{aligned}
$$

**Block (circuit) diagram**
```text
   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = Q2'   K0 = 1
J1 = Q0    K1 = Q0
J2 = Q1.Q0 K2 = 1
```
Unused states: 101 → 010, 110 → 010, 111 → 000, so the counter is self-starting.

**Timing diagram**
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|___________|‾‾‾
Q0   ____|‾‾‾|___|‾‾‾|_______|‾‾‾|___
Cnt  0    1   2   3   4   0   1   2
```
$Q_2$ is high for one clock period out of five, so it divides the clock frequency by 5.

#### Applications of counters
- Frequency division (divide-by-N), e.g. getting 1 Hz from 50 Hz in clocks.
- Digital clocks, watches and timers.
- Counting events or objects (production lines, people counters).
- Frequency counters and digital meters.
- Counter-type (digital-ramp) and dual-slope ADCs.
- Program counter and address generation in computers.
- Generating control sequences and timing signals.

#### Applications of shift registers
- Serial-to-parallel and parallel-to-serial data conversion (UART, serial communication).
- Temporary data storage and time delay.
- Ring and Johnson counters, sequence generators.
- Multiplication and division by 2 (shift left / right).
- Pseudo-random sequence generation (LFSR) and error checking (CRC).
- Keyboard scanning and display multiplexing.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many JK flip-flops does a MOD-5 synchronous counter need and which are don't care states?
   A. 3 flip-flops; 101, 110, 111
   B. 5 flip-flops; none
   C. 2 flip-flops; none
   D. 3 flip-flops; 011, 100
   Answer: A. 2^3 = 8 >= 5 gives 3 flip-flops; the 3 unused states 101, 110 and 111 are don't cares. (Key point: MOD-5 design basics)

2. Which equations are correct for the MOD-5 counter?
   A. J2 = Q1Q0, K2 = 1, J1 = K1 = Q0, J0 = Q2', K0 = 1
   B. J2 = Q0, K2 = Q0, J1 = K1 = 1, J0 = Q2, K0 = 1
   C. J2 = Q1, K2 = 0, J1 = K1 = Q0, J0 = K0 = 1
   D. J2 = Q1Q0, K2 = Q2, J1 = Q0, K1 = 1, J0 = 1, K0 = Q2'
   Answer: A. Q2 sets at 011 and resets at 100 (K2 = 1); J0 = Q2' stops Q0 from setting at 100 and K0 = 1 resets it. (Key point: MOD-5 equations)

3. What does the Q2 output show about this counter?
   A. It divides the clock frequency by 5
   B. It divides the clock frequency by 3
   C. It is high for 3 clock periods
   D. It equals the clock
   Answer: A. Q2 is high for one clock period in every five, so it is divide-by-5. (Key point: Frequency division)

4. Which is an application of counters?
   A. Serial-to-parallel conversion
   B. Frequency division and digital clocks
   C. LFSR pseudo-random generation
   D. Time delay of serial data
   Answer: B. Counters divide frequency and drive clocks, timers, and event counters; the others are shift-register uses. (Key point: Counter application)

## Related in Digital Logic

- [Mod-6 synchronous up counter using T](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-synchronous-t) — Digital Logic, chapter 8, asked 4×
- [Mod-5 synchronous up counter using SR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-sync-sr) — Digital Logic, chapter 8, asked 5×
- [Counter; MOD-6 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acounter-mod6-synchronous) — Digital Logic, chapter 8, asked 3×
- [Sync vs async; MOD-10 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-synchronous-counter) — Digital Logic, chapter 8, asked 2×
- [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8
- [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3×

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- [Short note: Shift register and counter](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ashort-note-shift-register-counter) — Basic Electronics Engineering, chapter 6