--- title: "Mod-5 synchronous up counter using SR" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:mod5-sync-sr" source: https://www.bctengineer.com/q/semester_3/digital_logic/mod5-sync-sr site: BCT Engineering --- # Mod-5 synchronous up counter using SR Digital Logic · Chapter 8: Counters - Asked in: 2080 Baisakh, 6+2 marks - Video: [MOD- 5 synchronous counter using JK flip flop](https://www.youtube.com/watch?v=HIozYLVhvQQ) — Learning with RACHIT MANCHANDA - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod5-sync-sr - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Design a synchronous mod-5 up-counter using SR flip-flops and draw its timing diagram. ## Short answer Three SR flip-flops with common clock. Equations: S2=Q1·Q0, R2=Q0'; S1=Q1'·Q0, R1=Q1·Q0; S0=Q2'·Q0', R0=Q0. Sequence: 000→001→010→011→100→000. Unused states 101→110→010 and 111→100 ensure self-starting operation. ## Answer A synchronous mod-5 up counter counts 000 → 001 → 010 → 011 → 100 → 000 with all flip-flops on one clock. Three SR flip-flops ($Q_2Q_1Q_0$) are needed ($2^3 = 8 \ge 5$); states 101, 110, 111 are don't cares. #### Step 1: SR excitation | Q → Q+ | S | R | |---|---|---| | 0 → 0 | 0 | X | | 0 → 1 | 1 | 0 | | 1 → 0 | 0 | 1 | | 1 → 1 | X | 0 | #### Step 2: Excitation table | Present Q2Q1Q0 | Next Q2Q1Q0 | S2 | R2 | S1 | R1 | S0 | R0 | |---|---|---|---|---|---|---|---| | 000 | 001 | 0 | X | 0 | X | 1 | 0 | | 001 | 010 | 0 | X | 1 | 0 | 0 | 1 | | 010 | 011 | 0 | X | X | 0 | 1 | 0 | | 011 | 100 | 1 | 0 | 0 | 1 | 0 | 1 | | 100 | 000 | 0 | 1 | 0 | X | 0 | X | #### Step 3: K-maps | S0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 1 | 0 | 0 | 1 | | 1 | 0 | X | X | X | | R0: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 0 | 1 | 1 | 0 | | 1 | X | X | X | X | | S1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 0 | 1 | 0 | X | | 1 | 0 | X | X | X | | R1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | X | 0 | 1 | 0 | | 1 | X | X | X | X | | S2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 0 | 0 | 1 | 0 | | 1 | 0 | X | X | X | | R2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | X | X | 0 | X | | 1 | 1 | X | X | X | For $R_2$, both $\overline{Q_1}$ and $\overline{Q_0}$ cover the 1-cell. With $R_2 = \overline{Q_1}$ the unused state 110 would hold itself forever (lock-out), so $R_2 = \overline{Q_0}$ is chosen. #### Step 4: Equations $$ \begin{aligned} &S_2 = Q_1Q_0,\quad R_2 = \overline{Q_0} \\ &S_1 = \overline{Q_1}Q_0,\quad R_1 = Q_1Q_0 \\ &S_0 = \overline{Q_2}\overline{Q_0},\quad R_0 = Q_0 \end{aligned} $$ S and R of each flip-flop are never 1 together in any state, so the forbidden input S = R = 1 never occurs. #### Step 5: Circuit diagram ```text +-----+ +-----+ +-----+ S0>|S Q|-Q0 S1>|S Q|-Q1 S2>|S Q|-Q2 | FF0 | | FF1 | | FF2 | R0>|R | R1>|R | R2>|R | +--o--+ +--o--+ +--o--+ | | | CLK---+-------------+-------------+ S0 = Q2'.Q0' R0 = Q0 S1 = Q1'.Q0 R1 = Q1.Q0 S2 = Q1.Q0 R2 = Q0' ``` Unused states: 101 → 110 → 010, 111 → 100, so the counter is self-starting. #### Step 6: Timing diagram ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q2 ________________|‾‾‾|___________ Q1 ________|‾‾‾‾‾‾‾|___________|‾‾‾ Q0 ____|‾‾‾|___|‾‾‾|_______|‾‾‾|___ Cnt 0 1 2 3 4 0 1 2 ``` $Q_2$ is high for one clock period in every five ($f_{clk}/5$). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What S and R inputs are needed for a transition Q 1 -> 0? A. S = 0, R = 1 B. S = 1, R = 0 C. S = X, R = 0 D. S = 0, R = X Answer: A. To reset the flip-flop, S must be 0 and R must be 1. (Key point: SR excitation) 2. Why is R2 = Q0' chosen instead of R2 = Q1'? A. Q1' needs more gates B. With R2 = Q1' the unused state 110 would hold itself forever (lock-out) C. Q0' gives a faster clock D. Q1' makes S and R both 1 Answer: B. R2 = Q1' keeps Q2 set in 110 and the machine would stay locked; R2 = Q0' lets it escape to a valid state. (Key point: Choice of R2) 3. What is guaranteed about S and R in this design? A. They are always equal B. S = R = 1 never occurs in any state C. R is always 1 D. S is always 0 during Q = 1 Answer: B. The excitation table never needs S and R both 1, so the forbidden input is avoided. (Key point: Forbidden input) 4. Why are 3 SR flip-flops used for the mod-5 counter? A. 2^2 = 4 < 5 and 2^3 = 8 >= 5 B. Because five needs five flip-flops C. Because SR flip-flops come in threes D. Because 5 is odd Answer: A. Two flip-flops give only 4 states; three give 8, enough for 5, with 101, 110, 111 as don't cares. (Key point: Number of flip-flops) ## Close variants set in other exams - [Mod-6 synchronous up counter using T](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-synchronous-t) — Digital Logic, chapter 8, asked 4× - [Counter; MOD-6 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acounter-mod6-synchronous) — Digital Logic, chapter 8, asked 3× ## Related in Digital Logic - [SR equation; mod-5 counter using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-equation-mod5-d-counter) — Digital Logic, chapter 8 - [Mod-5 Gray code synchronous up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-gray-sync-counter) — Digital Logic, chapter 8 - [BCD synchronous counter using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-synchronous-counter-t) — Digital Logic, chapter 8 - [Mod-5 synchronous counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-synchronous-jk) — Digital Logic, chapter 8, asked 4× - [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8