--- title: "Mod-5 synchronous counter using JK" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:mod5-synchronous-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/mod5-synchronous-jk site: BCT Engineering --- # Mod-5 synchronous counter using JK Digital Logic · Chapter 8: Counters - Asked in: 2081 Bhadra, 7 marks; 2080 Bhadra, 7 marks; 2076 Asoj (asked 3 times) - Video: [MOD- 5 synchronous counter using JK flip flop](https://www.youtube.com/watch?v=HIozYLVhvQQ) — Learning with RACHIT MANCHANDA - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod5-synchronous-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Design a mod-5 synchronous counter using positive edge-triggered JK flip flops. ## Short answer Use three JK flip-flops. J2 = Q1 Q0, K2 = 1; J1 = Q0, K1 = Q0; J0 = Q2', K0 = 1. The counter runs through states 000 to 100 and is self-starting. ## Answer A **mod-5 synchronous counter** counts 0, 1, 2, 3, 4 and returns to 0 (5 states). Since $2^2 < 5 \le 2^3$, **3 flip-flops** (Q2 Q1 Q0, Q2 = MSB) are needed. All flip-flops get the same clock (positive edge triggered J-K), and the J, K inputs are found from the excitation table. #### Step 1: state diagram ```text 000 -> 001 -> 010 -> 011 -> 100 ^ | +----------------------------+ Unused: 101, 110, 111 (don't cares) ``` #### Step 2: J-K excitation table | Q | Q+ | J | K | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | x | | 1 | 0 | x | 1 | | 1 | 1 | x | 0 | #### Step 3: state table with flip-flop inputs | State | Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ | J2 | K2 | J1 | K1 | J0 | K0 | |---|---|---|---|---|---|---|---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | x | 0 | x | 1 | x | | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | x | 1 | x | x | 1 | | 2 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | x | x | 0 | 1 | x | | 3 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | x | x | 1 | x | 1 | | 4 | 1 | 0 | 0 | 0 | 0 | 0 | x | 1 | 0 | x | 0 | x | States 5, 6 and 7 never occur, so all their inputs are don't cares (x). #### Step 4: K-maps and simplified expressions ```text K-map for J2 Q2\Q1Q0 00 01 11 10 0 0 0 1 0 1 x x x x K-map for K2 Q2\Q1Q0 00 01 11 10 0 x x x x 1 1 x x x K-map for J1 Q2\Q1Q0 00 01 11 10 0 0 1 x x 1 0 x x x K-map for K1 Q2\Q1Q0 00 01 11 10 0 x x 1 0 1 x x x x K-map for J0 Q2\Q1Q0 00 01 11 10 0 1 x x 1 1 0 x x x K-map for K0 Q2\Q1Q0 00 01 11 10 0 x 1 1 x 1 x x x x ``` $$ \begin{aligned} J_2 &= Q_1 Q_0, & K_2 &= 1 \\ J_1 &= Q_0, & K_1 &= Q_0 \\ J_0 &= \overline{Q_2}, & K_0 &= 1 \end{aligned} $$ #### Step 5: logic diagram ```text +--------+ +--------+ +--------+ J0->|J0 Q0 |J1->|J1 Q1 |J2->|J2 Q2 | K0->|K0 Q0' |K1->|K1 Q1' |K2->|K2 Q2' | |> FF0 | |> FF1 | |> FF2 | +--------+ +--------+ +--------+ CLK ---^-------------^-------------^ Input connections: J0 <- Q2' K0 <- 1 (HIGH) J1 <- Q0 K1 <- Q0 J2 <- AND(Q1, Q0) K2 <- 1 (HIGH) ``` #### Timing diagram ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Q0 _|‾‾‾|___|‾‾‾|_______|‾‾‾|__ Q1 _____|‾‾‾‾‾‾‾|___________|‾‾ Q2 _____________|‾‾‾|__________ ``` The counter goes 000, 001, 010, 011, 100, 000, ...; Q2 is high for one clock in five, so the output frequency is $f_{CLK}/5$. **Unused states check:** with these equations, 101 goes to 010, 110 goes to 010 and 111 goes to 000, so the counter returns to the main sequence by itself (self-starting). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why does a mod-5 counter need 3 flip-flops? A. Because 2^2 = 4 < 5 <= 2^3 = 8 B. Because 5 is odd C. Because 5 states need 5 flip-flops D. Because 2^3 = 8 equals 5 + 3 Answer: A. Two flip-flops give only 4 states, so the smallest n with 2^n >= 5 is 3. (Key point: Number of flip-flops) 2. How are unused states 101, 110 and 111 treated in the K-maps? A. As zeros B. As ones C. As don't cares (x), to simplify the expressions D. They are removed by a reset Answer: C. Those states never occur, so their J and K entries are don't cares, which lets the K-maps simplify. (Key point: Unused states as don't cares) 3. Which set of equations results for the mod-5 counter? A. J2 = Q1 Q0, K2 = 1; J1 = K1 = Q0; J0 = Q2', K0 = 1 B. J2 = Q1 + Q0, K2 = 0; J1 = K1 = Q0'; J0 = Q2, K0 = 0 C. J2 = Q2', K2 = 1; J1 = K1 = 1; J0 = Q1 Q0, K0 = 1 D. J2 = K2 = Q1 Q0; J1 = Q0, K1 = 1; J0 = K0 = 1 Answer: A. The K-maps give J2 = Q1Q0, K2 = 1, J1 = K1 = Q0, J0 = Q2' and K0 = 1. (Key point: Simplified JK equations) 4. With these equations, what does the unused state 111 go to on the next clock? A. 111 (it locks up) B. 010 C. 100 D. 000 Answer: D. From 111: J2=1,K2=1 toggles Q2 to 0; J1=K1=1 toggles Q1 to 0; K0=1 clears Q0, giving 000, so the counter is self-starting. (Key point: Self-starting check) ## Close variants set in other exams - [MOD-6 synchronous counter, negative edge JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-negative-edge) — Digital Logic, chapter 8, asked 4× ## Related in Digital Logic - [Mod-10 negative edge ripple counter with JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-ripple-jk-negative-edge) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter, positive edge](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-t-positive) — Digital Logic, chapter 8, asked 3× - [SR equation; mod-5 counter using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-equation-mod5-d-counter) — Digital Logic, chapter 8 - [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8 - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [Edge triggered JK flip-flop circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-circuit) — Digital Logic, chapter 6 ## Related in other subjects - [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6