---
title: "Sync vs async; mod-6 synchronous counter (JK)"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:mod6-sync-jk-compare"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mod6-sync-jk-compare
site: BCT Engineering
---

# Sync vs async; mod-6 synchronous counter (JK)

Digital Logic · Chapter 8: Counters

- Asked in: 2079 Bhadra, 2+7 marks
- Video: [Design of Synchronous Counter: Design of MOD-6 Synchronous counter using JK Flip Flop](https://www.youtube.com/watch?v=HhvtfKsoJCY) — Engg-Course-Made-Easy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod6-sync-jk-compare
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Differentiate between synchronous and asynchronous counters. Design a mod-6 synchronous counter using JK flip-flops.

## Short answer

Synchronous counters have a common clock, so all flip-flops change simultaneously, offering high speed and no ripple delay. Asynchronous (ripple) counters cascade the clock, causing propagation delays. A MOD-6 synchronous counter uses states 000–101 with J0=K0=1, J1=Q2'Q0, K1=Q0, J2=Q1Q0, K2=Q0, and is self-starting.

## Answer

#### Synchronous vs asynchronous counters
| Point | Synchronous counter | Asynchronous (ripple) counter |
|---|---|---|
| Clock | Common clock to all flip-flops | Only FF0 gets the clock; each next FF is clocked by the previous output |
| Change of state | All flip-flops change together | Flip-flops change one after another (ripple) |
| Delay | One FF delay + gate delay | Adds up: $n \times t_{pd}$ |
| Speed | Fast, high clock frequency | Slow, frequency falls as $n$ grows |
| Circuit | Needs extra gating logic | Simple, few or no extra gates |
| Decoding glitches | None (no false states) | Momentary false states give glitches |
| Example ICs | 74160/74163, 74190 | 7490, 7493 |

#### Design of mod-6 synchronous counter (JK flip-flops)
**Step 1: States.** 000 → 001 → 010 → 011 → 100 → 101 → 000. Since $2^3 = 8 \ge 6$, three JK flip-flops ($Q_2Q_1Q_0$) with a common clock are used. 110 and 111 are don't cares.

**Step 2: Excitation table** (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

| Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 010 | 0 | X | 1 | X | X | 1 |
| 010 | 011 | 0 | X | X | 0 | 1 | X |
| 011 | 100 | 1 | X | X | 1 | X | 1 |
| 100 | 101 | X | 0 | 0 | X | 1 | X |
| 101 | 000 | X | 1 | 0 | X | X | 1 |

**Step 3: K-maps**

| J1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | X | X |
| 1 | 0 | 0 | X | X |

| K1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 1 | 0 |
| 1 | X | X | X | X |

| J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | X | X | X | X |

| K2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | X | X |
| 1 | 0 | 1 | X | X |

$J_0 = K_0 = 1$ since $Q_0$ toggles every clock.

**Step 4: Equations**
$$
\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = Q_0 \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}
$$

**Step 5: Circuit diagram**
```text
   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = Q2'.Q0    K1 = Q0
J2 = Q1.Q0     K2 = Q0
```

**Step 6: Unused states:** 110 → 111 → 000, so the counter is self-starting.

**Step 7: Timing diagram**
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   0   1
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How does propagation delay differ in synchronous vs asynchronous counters?
   A. Synchronous: one FF delay plus gate delay; asynchronous: n x tpd
   B. Both are n x tpd
   C. Synchronous: n x tpd; asynchronous: one delay
   D. Both are one FF delay
   Answer: A. In a ripple counter each stage waits for the previous one, so delays add up. (Key point: Sync vs async delay)

2. For a JK flip-flop transition 1 -> 0, which inputs are required?
   A. J = 1, K = X
   B. J = 0, K = X
   C. J = X, K = 1
   D. J = X, K = 0
   Answer: C. To go 1 to 0 we can use reset (J=0,K=1) or toggle (J=1,K=1), so J is a don't care and K = 1. (Key point: JK excitation)

3. Which equations result for the MOD-6 JK counter?
   A. J2 = Q1Q0, K2 = Q0, J1 = Q2'Q0, K1 = Q0, J0 = K0 = 1
   B. J2 = Q1, K2 = Q0, J1 = Q0, K1 = Q0, J0 = K0 = 1
   C. J2 = Q1Q0, K2 = 1, J1 = Q0, K1 = Q2, J0 = K0 = 0
   D. J2 = Q2Q0, K2 = Q1, J1 = Q2'Q0, K1 = 1, J0 = K0 = 1
   Answer: A. From the K-maps with don't cares: J2 = Q1Q0, K2 = Q0, J1 = Q2'Q0, K1 = Q0, and Q0 toggles each clock. (Key point: MOD-6 JK equations)

4. Where does unused state 110 go on the next clock?
   A. 000
   B. 101
   C. 111
   D. 110
   Answer: C. With J2 = 0, K2 = 0, J1 = 0, K1 = 0 and J0 = K0 = 1, only Q0 toggles, giving 111, which then goes to 000. (Key point: Self-start)

## Related in Digital Logic

- [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3×
- [Sync vs async; MOD-10 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-synchronous-counter) — Digital Logic, chapter 8, asked 2×
- [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8
- [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8
- [Sync vs async; 3-bit synchronous up counter (T)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-up-counter-3bit-t) — Digital Logic, chapter 8
- [Mod-5 synchronous counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-synchronous-jk) — Digital Logic, chapter 8, asked 4×

## Related in other subjects

- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×