---
title: "MOD-6 synchronous counter, negative edge JK"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:mod6-sync-jk-negative-edge"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mod6-sync-jk-negative-edge
site: BCT Engineering
---

# MOD-6 synchronous counter, negative edge JK

Digital Logic · Chapter 8: Counters

- Asked in: 2078 Kartik, 6 marks
- Video: [Design MOD 6 Counter  Using  JK FLIP FLOP | MOD 6 Up COUNTER | MOD 6 SYNCHRONOUS COUNTER USING JK FF](https://www.youtube.com/watch?v=uZm4s5gPM3g) — Techno Tutorials ( e-Learning)
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod6-sync-jk-negative-edge
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Design the synchronous MOD-6 counter using -ve edge triggered JK flip flop.

## Short answer

A MOD-6 synchronous counter with negative-edge JK flip-flops shares a common clock. States are 000–101; equations: J0=K0=1, J1=Q2'Q0, K1=Q0, J2=Q1Q0, K2=Q0. Unused states 110 and 111 transition to 000, making the counter self-starting.

## Answer

A synchronous MOD-6 counter goes through 6 states, 000 → 001 → 010 → 011 → 100 → 101 → 000, with all flip-flops triggered by the **falling edge** of a common clock. Three JK flip-flops are needed ($2^3 = 8 \ge 6$). States 110 and 111 are not used (don't cares).

#### Excitation table
JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

| Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 010 | 0 | X | 1 | X | X | 1 |
| 010 | 011 | 0 | X | X | 0 | 1 | X |
| 011 | 100 | 1 | X | X | 1 | X | 1 |
| 100 | 101 | X | 0 | 0 | X | 1 | X |
| 101 | 000 | X | 1 | 0 | X | X | 1 |

#### K-maps
| J1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | X | X |
| 1 | 0 | 0 | X | X |

| K1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 1 | 0 |
| 1 | X | X | X | X |

| J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | X | X | X | X |

| K2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | X | X |
| 1 | 0 | 1 | X | X |

$J_0 = K_0 = 1$ (Q0 toggles on every clock).

#### Equations
$$
\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = Q_0 \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}
$$

#### Circuit (negative-edge triggered)
```text
   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = Q2'.Q0    K1 = Q0
J2 = Q1.Q0     K2 = Q0
```
"o" at the clock input shows negative-edge triggering. Only two 2-input AND gates are needed.

#### Check
Unused states go 110 → 111 → 000, so the counter starts correctly from any power-on state.

#### Timing diagram
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   0   1
```
All outputs change at the falling clock edges; $Q_2$ gives $f_{clk}/6$.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does negative-edge triggering mean for this counter?
   A. Outputs change on the rising edge of the clock
   B. All flip-flops change on the falling edge of the common clock
   C. Outputs change when the clock is low
   D. Each FF is clocked by the previous stage
   Answer: B. The 'o' at the clock input shows that all flip-flops change at the falling edge of the common clock. (Key point: Negative-edge triggering)

2. For a JK flip-flop transition 0 -> 1, what are J and K?
   A. J = 1, K = X
   B. J = 0, K = X
   C. J = X, K = 1
   D. J = X, K = 0
   Answer: A. To set the flip-flop J = 1 and K may be anything (set or toggle). (Key point: Excitation of 0 -> 1)

3. Which are the correct equations for J2, K2, J1, K1?
   A. J2 = Q1Q0, K2 = Q0, J1 = Q2'Q0, K1 = Q0
   B. J2 = Q1, K2 = Q1, J1 = Q2, K1 = Q0
   C. J2 = Q0, K2 = Q1, J1 = Q0, K1 = Q2
   D. J2 = Q2'Q0, K2 = Q1Q0, J1 = Q0, K1 = 1
   Answer: A. J1 uses Q2' so FF1 does not toggle at count 5; J2 = Q1Q0 sets Q2 at 011; K2 = Q0 resets it at 101. (Key point: Equations)

4. What does Q2 give relative to the clock frequency?
   A. f_clk/3
   B. f_clk/8
   C. f_clk/6
   D. f_clk/2
   Answer: C. Q2 completes one cycle for every 6 clock pulses, so f_clk/6. (Key point: Frequency division)

## Close variants set in other exams

- [Mod-5 synchronous counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-synchronous-jk) — Digital Logic, chapter 8, asked 4×

## Related in Digital Logic

- [Mod-10 negative edge ripple counter with JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-ripple-jk-negative-edge) — Digital Logic, chapter 8
- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×
- [Edge triggered JK flip-flop circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-circuit) — Digital Logic, chapter 6
- [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6
- [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6
- [Parallel counter; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-up-jk-parallel) — Digital Logic, chapter 8

## Related in other subjects

- [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6
- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9