---
title: "Parallel counter; mod-6 synchronous counter (JK)"
subject: "Digital Logic"
chapter: 8
key: "semester_3/digital_logic:mod6-sync-up-jk-parallel"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mod6-sync-up-jk-parallel
site: BCT Engineering
---

# Parallel counter; mod-6 synchronous counter (JK)

Digital Logic · Chapter 8: Counters

- Asked in: 2078 Bhadra, 1+7 marks
- Video: [171 Design of Synchronous MOD   6 Counter](https://www.youtube.com/watch?v=LLNuPfDS6UQ) — SP Engg. ACADEMY
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod6-sync-up-jk-parallel
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8

## Question

Define parallel counter. Design a mod-6 synchronous up counter using JK flip flop.

## Short answer

A parallel (synchronous) counter applies the clock to all flip-flops simultaneously. A mod-6 synchronous up counter with 3 JK flip-flops has J2=Q1Q0, K2=Q0, J1=Q2'Q0, K1=Q0, J0=K0=1; it is self-starting.

## Answer

#### Parallel counter
A **parallel counter** is another name for a **synchronous counter**: the clock is applied to all flip-flops in parallel, so they all change state at the same instant. Gates at the J-K (or T/D) inputs decide which flip-flops toggle.

#### Design: mod-6 synchronous up counter (JK)
**Step 1: States.** A mod-6 counter counts 0 to 5 (000 to 101) and returns to 000. $2^3 = 8 \ge 6$, so 3 JK flip-flops ($Q_2Q_1Q_0$) are used. Unused states 110 and 111 are don't cares.

**Step 2: Excitation table** (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

| Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 010 | 0 | X | 1 | X | X | 1 |
| 010 | 011 | 0 | X | X | 0 | 1 | X |
| 011 | 100 | 1 | X | X | 1 | X | 1 |
| 100 | 101 | X | 0 | 0 | X | 1 | X |
| 101 | 000 | X | 1 | 0 | X | X | 1 |

**Step 3: K-maps**

| J1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | X | X |
| 1 | 0 | 0 | X | X |

| K1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 1 | 0 |
| 1 | X | X | X | X |

| J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | X | X | X | X |

| K2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | X | X |
| 1 | 0 | 1 | X | X |

$J_0 = K_0 = 1$ since $Q_0$ toggles on every clock.

**Step 4: Equations**
$$
\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = Q_0 \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}
$$

**Step 5: Circuit diagram**
```text
   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = Q2'.Q0     K1 = Q0
J2 = Q1.Q0      K2 = Q0
```
Two 2-input AND gates are needed.

**Step 6: Unused states**
| Unused state | Next state |
|---|---|
| 110 | 111 |
| 111 | 000 |

So the counter is self-starting.

**Step 7: Timing diagram**
```text
CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   0   1
```
All outputs change together at the falling clock edge; $Q_2$ gives $f_{clk}/6$.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is a parallel counter?
   A. A counter with parallel data load only
   B. Another name for a synchronous counter, with the clock applied to all flip-flops in parallel
   C. A ripple counter with two chains
   D. A counter that counts two sequences at once
   Answer: B. A parallel counter is a synchronous counter: all flip-flops get the same clock and change at the same instant. (Key point: Parallel counter)

2. How many JK flip-flops does a mod-6 counter need and which states are don't cares?
   A. 3 flip-flops; 110 and 111
   B. 2 flip-flops; none
   C. 3 flip-flops; 101 and 110
   D. 6 flip-flops; none
   Answer: A. 2^3 = 8 >= 6 gives 3 flip-flops. States 110 and 111 are never used, so they are don't cares. (Key point: Flip-flops and don't cares)

3. Which are the correct input equations for the mod-6 up counter?
   A. J2 = Q1Q0, K2 = Q0, J1 = Q2'Q0, K1 = Q0, J0 = K0 = 1
   B. J2 = Q1, K2 = Q1, J1 = Q0, K1 = Q0, J0 = K0 = 1
   C. J2 = Q1Q0, K2 = 1, J1 = Q0, K1 = Q0, J0 = K0 = 0
   D. J2 = Q2'Q0, K2 = Q0, J1 = Q1Q0, K1 = Q0, J0 = K0 = 1
   Answer: A. Q1 must not set at 5 to 0 (Q2 = 1 blocks it, J1 = Q2'Q0), Q2 sets at 3 to 4 and resets at 5 to 0 (K2 = Q0). (Key point: Mod-6 equations)

4. What happens if the mod-6 counter powers up in unused state 110?
   A. It stays in 110 forever
   B. It goes to 111 and then to 000, so it is self-starting
   C. It goes to 101
   D. It goes to 000 directly
   Answer: B. With the derived equations 110 goes to 111 and 111 goes to 000, re-entering the valid sequence. (Key point: Self-starting check)

## Related in Digital Logic

- [MOD-6 synchronous counter, negative edge JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-negative-edge) — Digital Logic, chapter 8, asked 4×
- [Mod-5 Gray code synchronous up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-gray-sync-counter) — Digital Logic, chapter 8
- [Mod-5 synchronous counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-synchronous-jk) — Digital Logic, chapter 8, asked 4×
- [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8
- [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8
- [Mod-5 synchronous up counter using SR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-sync-sr) — Digital Logic, chapter 8, asked 5×

## Related in other subjects

- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9
- [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9