--- title: "Mod-6 synchronous up counter using T" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:mod6-synchronous-t" source: https://www.bctengineer.com/q/semester_3/digital_logic/mod6-synchronous-t site: BCT Engineering --- # Mod-6 synchronous up counter using T Digital Logic · Chapter 8: Counters - Asked in: 2082 Shrawan, 7 marks; 2081 Bhadra, 7 marks; 2075 Chaitra, 7 marks (asked 3 times) - Video: [MOD 6 Synchronous Counter Using T Flip Flop | MOD 6 Counter | Counter Using T Flip Flop](https://www.youtube.com/watch?v=pvl1_RQ-CDc) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mod6-synchronous-t - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Design a mod-6 synchronous counter using T Flip-Flops with timing diagrams. ## Short answer Use three T flip-flops. T0 = 1, T1 = Q0 Q2', T2 = Q0 (Q1 + Q2). The counter sequences 000 to 101 and self-corrects from unused states. ## Answer A **mod-6 synchronous counter** goes through 6 states, 0 to 5 (000 to 101), and then returns to 000. Since $2^2 < 6 \le 2^3$, **3 T flip-flops** (Q2 Q1 Q0, Q2 = MSB) with a common clock are used. A T flip-flop must have T = 1 whenever its output has to change. #### Step 1: state diagram ```text 000 -> 001 -> 010 -> 011 -> 100 -> 101 ^ | +-----------------------------------+ Unused: 110, 111 (don't cares) ``` #### Step 2: T excitation table | Q | Q+ | T | |---|---|---| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 | #### Step 3: state table with flip-flop inputs | State | Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ | T2 | T1 | T0 | |---|---|---|---|---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | | 2 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | 3 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | | 4 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | #### Step 4: K-maps ```text K-map for T2 Q2\Q1Q0 00 01 11 10 0 0 0 1 0 1 0 1 x x K-map for T1 Q2\Q1Q0 00 01 11 10 0 0 1 1 0 1 0 0 x x K-map for T0 Q2\Q1Q0 00 01 11 10 0 1 1 1 1 1 1 1 x x ``` - $T_0$: all used states are 1, so $T_0 = 1$. - $T_1$: 1s at states 1 and 3; state 5 is 0, so $T_1 = Q_0 \overline{Q_2}$. - $T_2$: 1s at states 3 and 5; with don't care 7: $T_2 = Q_1 Q_0 + Q_2 Q_0$. $$ \begin{aligned} T_0 &= 1 \\ T_1 &= Q_0\,\overline{Q_2} \\ T_2 &= Q_0 Q_1 + Q_0 Q_2 = Q_0 (Q_1 + Q_2) \end{aligned} $$ #### Step 5: logic diagram ```text 1 T1 T2 | | | +----+ +----+ +----+ |T0 | |T1 | |T2 | | FF0|--Q0 | FF1|--Q1 | FF2|--Q2 |> | |> | |> | +----+ +----+ +----+ ^ ^ ^ CLK ---------+-------------+ (common clock) T1 = Q0 AND Q2' : one 2-input AND T2 = Q0.Q1 + Q0.Q2 : two ANDs + one OR (= Q0 AND (Q1 OR Q2)) ``` #### Timing diagram ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Q0 _|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾ Q1 _____|‾‾‾‾‾‾‾|______________ Q2 _____________|‾‾‾‾‾‾‾|______ ``` The output sequence is 000, 001, 010, 011, 100, 101, 000, ...; Q2 is high for two clocks out of six, so its frequency is $f_{CLK}/6$. **Unused states:** 110 goes to 111 and 111 goes to 010, so the counter enters the main count by itself (self-starting). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. For a T flip-flop, when must T be 1? A. When the next state is 1 B. When the present state is 1 C. When the flip-flop output must change D. When the clock is high Answer: C. T = Q xor Q+, so T = 1 whenever the output has to change. (Key point: T excitation rule) 2. Why is T0 = 1 for the mod-6 counter? A. Q0 changes at every clock in all used states B. Q0 never changes C. Because Q0 depends on Q2 D. Because 110 and 111 are used states Answer: A. The LSB toggles at every count (0,1,0,1,0,1), so T0 = 1 in all used states. (Key point: T0 value) 3. Which equations are obtained for T1 and T2? A. T1 = Q0 Q2, T2 = Q1 + Q0 B. T1 = Q0 Q2', T2 = Q0 (Q1 + Q2) C. T1 = Q0', T2 = Q1 Q0 D. T1 = Q2', T2 = Q2 Q1 Answer: B. T1 is 1 at states 1 and 3 but 0 at state 5, giving Q0Q2'; T2 is 1 at 3 and 5 giving Q0Q1 + Q0Q2. (Key point: T1 and T2 equations) 4. What does the unused state 110 go to on the next clock? A. 000 B. 111 C. 101 D. 110 Answer: B. At 110, T0 = 1 toggles Q0 to 1, T1 = 0 and T2 = 0 hold the rest, so 110 goes to 111, then 111 goes to 010. (Key point: Self-start from unused states) ## Close variants set in other exams - [Mod-5 synchronous up counter using SR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-sync-sr) — Digital Logic, chapter 8, asked 5× ## Related in Digital Logic - [Mod-5 Gray code synchronous up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-gray-sync-counter) — Digital Logic, chapter 8 - [SR equation; mod-5 counter using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-equation-mod5-d-counter) — Digital Logic, chapter 8 - [BCD synchronous counter using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-synchronous-counter-t) — Digital Logic, chapter 8 - [Mod-5 synchronous counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-synchronous-jk) — Digital Logic, chapter 8, asked 4× - [Sync vs async; mod-6 synchronous counter (JK)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-compare) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8 ## Related in other subjects - [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×