---
title: "Multiplexing display concept and operation"
subject: "Digital Logic"
chapter: 11
key: "semester_3/digital_logic:multiplexing-display"
source: https://www.bctengineer.com/q/semester_3/digital_logic/multiplexing-display
site: BCT Engineering
---

# Multiplexing display concept and operation

Digital Logic · Chapter 11: Applications

- Asked in: 2081 Bhadra, 5 marks; 2080 Bhadra, 4 marks; 2080 Baisakh, 4 marks; 2079 Bhadra, 5 marks; 2078 Kartik, 5 marks (asked 5 times)
- Video: [Multiplexing (for beginners) - Ec-Projects](https://www.youtube.com/watch?v=rOAzENzgA8U) — EcProjects
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/multiplexing-display
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-11

## Question

Explain the concept of the multiplexing display. Illustrate with a suitable diagram to support your explanation.

## Short answer

Multiplexed display shares one BCD-to-7-segment decoder and segment lines among multiple digits, enabling one digit at a time via digit-select transistors. A counter cycles through digits rapidly; persistence of vision makes all appear lit. This reduces wiring and IC count.

## Answer

A **multiplexed display** drives several 7-segment digits by sharing one set of segment lines (a–g) and one BCD-to-7-segment decoder among all digits, and switching the digits on **one at a time** in rapid sequence. Because each digit is refreshed faster than the eye can follow (persistence of vision), all digits appear to be lit continuously.

#### Need for multiplexing
- A non-multiplexed 4-digit display needs 4 decoders and $4 \times 7 = 28$ segment lines.
- A multiplexed display needs only **1 decoder**, **7 segment lines** and **4 digit-select lines** (11 lines in total).
- Fewer ICs, less wiring, lower power (only one digit draws current at a time).

#### Block diagram
```text
 BCD digit 0 ─┐
 BCD digit 1 ─┤ 4-bit    BCD  BCD-to-7  a..g
 BCD digit 2 ─┤ 4:1 MUX ────> segment ─────┬──┬──┬──┐
 BCD digit 3 ─┘ (x4)          decoder      │  │  │  │
                  ^                       [D3][D2][D1][D0]
                  │ S1 S0                  ^   ^   ^   ^
 Clock ─> 2-bit ──┴──> 2-to-4 decoder ─────┴───┴───┴───┘
 (~1 kHz) counter      (one digit enabled at a time)
```
The segment lines a–g of all four displays are wired in parallel. Each display's common cathode (or common anode) is driven separately through a transistor by one output of the 2-to-4 decoder.

#### Operation
1. A clock (typically 100 Hz – 1 kHz) drives a 2-bit counter that cycles 00, 01, 10, 11.
2. The counter output selects one BCD digit through the data multiplexer and sends it to the single BCD-to-7-segment decoder.
3. The same counter output goes to a 2-to-4 decoder, which enables only the matching display (e.g. count 00 turns on D0).
4. So during the first time slot, digit 0's code appears on the segment lines and only D0 glows; in the next slot digit 1's code appears and only D1 glows, and so on.
5. Each digit is ON for 1/4 of the cycle (duty cycle 25%). If the full scan repeats at more than about 50 times per second, no flicker is seen.
6. Since each digit is ON only part of the time, a higher peak current is given to keep the brightness the same.

#### Example
To show **2025**: in slot 0 the code for 5 is sent and D0 lights; slot 1 sends 2 to D1; slot 2 sends 0 to D2; slot 3 sends 2 to D3. Scanning at 1 kHz gives each digit 250 refreshes per second, so the eye sees "2025" steadily.

Multiplexed displays are used in digital clocks, frequency counters, calculators and digital meters.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the core idea of a multiplexed display?
   A. Each digit has its own decoder
   B. Segment lines and one decoder are shared, and digits are switched ON one at a time rapidly
   C. All digits are lit at the same time with different decoders
   D. Digits are lit only once
   Answer: B. Sharing the decoder and segment lines while scanning digits quickly makes all digits appear lit due to persistence of vision. (Key point: Concept)

2. For a 4-digit display, how many lines are needed with multiplexing?
   A. 28 segment lines
   B. 7 segment lines plus 4 digit-select lines (11 total) with 1 decoder
   C. 4 decoders and 4 select lines
   D. 14 lines
   Answer: B. Non-multiplexed needs 4 x 7 = 28 segment lines and 4 decoders. Multiplexed needs 1 decoder, 7 + 4 = 11 lines. (Key point: Saving in lines)

3. What does the counter drive in the multiplexer circuit?
   A. Only the clock
   B. Both the data multiplexer select (choosing the digit's BCD) and the 2-to-4 decoder (enabling the matching display)
   C. Only the decoder IC
   D. The Schmitt trigger
   Answer: B. The same count selects the digit's BCD code and enables the matching display so code and digit stay in step. (Key point: Scan operation)

4. With 4 digits, what is each digit's duty cycle, and what is needed to keep brightness?
   A. 50%, lower current
   B. 25%, higher peak current
   C. 100%, normal current
   D. 25%, lower current
   Answer: B. Each digit is ON for 1/4 of the cycle, so a higher peak current is given to keep the brightness the same. Refresh must exceed about 50 Hz to avoid flicker. (Key point: Refresh and brightness)

## Related in Digital Logic

- [Frequency counter operation with block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afrequency-counter) — Digital Logic, chapter 11, asked 14×
- [SR drawbacks; D flip-flop operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-d-flipflop) — Digital Logic, chapter 6
- [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7
- [Operation of a digital clock](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adigital-clock-operation) — Digital Logic, chapter 8
- [CMOS inverter operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-inverter) — Digital Logic, chapter 10
- [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9×

## Related in other subjects

- [Circular queue with display operation](https://www.bctengineer.com/question.md?key=semester_4%2Fdata_structure_and_algorithm%3Acircular-queue-enqueue-dequeue-display) — Data Structure and Algorithm, chapter 2
- [Data logger block diagram and operation](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adl-block) — Instrumentation II, chapter 5, asked 6×
- [PID control operation with block diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Apid-operation-block-diagram) — Embedded System, chapter 7, asked 4×
- [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2
