---
title: "Multiplexer tree; 16:1 MUX from 4:1"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:mux-16to1-from-4to1"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-16to1-from-4to1
site: BCT Engineering
---

# Multiplexer tree; 16:1 MUX from 4:1

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2074 Asoj, 1+4 marks
- Video: [16 to 1 mux using 4 to 1 mux | 16 X 1 MULTIPLEXER USING 4 TO 1 MULTIPLEXER](https://www.youtube.com/watch?v=3lUHu4AYqWk) — Aasaan padhaai
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-16to1-from-4to1
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

What is a multiplexer tree? Design the 16 to 1 multiplexer using 4 to 1 multiplexer.

## Short answer

A multiplexer tree cascades smaller MUXes. To build a 16:1 MUX, use four 4:1 MUxes in the first level with selects S1S0 grouping I0–I15, and one 4:1 MUX in the second level with selects S3S2 to pick the final output.

## Answer

#### Multiplexer tree

A **multiplexer tree** is the connection of small multiplexers in levels to make a larger multiplexer. The first level selects within groups using the lower select bits, and the next level selects one group using the higher select bits.

#### 16:1 MUX from 4:1 MUXes

A 16:1 MUX has inputs $I_0$–$I_{15}$ and four select lines $S_3S_2S_1S_0$. Use five 4:1 MUXes:

- **Level 1:** four 4:1 MUXes (M1–M4) with selects $S_1S_0$. M1 gets $I_0$–$I_3$, M2 gets $I_4$–$I_7$, M3 gets $I_8$–$I_{11}$, M4 gets $I_{12}$–$I_{15}$.
- **Level 2:** one 4:1 MUX (M5) with selects $S_3S_2$ picks one of the outputs of M1–M4.

```text
             S1 S0
 I0-I3   -->[ M1 ]--Y1--+
 I4-I7   -->[ M2 ]--Y2--+--> I0..I3 of
 I8-I11  -->[ M3 ]--Y3--+    [ M5 ] ----> Y
 I12-I15 -->[ M4 ]--Y4--+     S3 S2
```

| $S_3S_2$ | M5 passes | Y for $S_1S_0$ = 00, 01, 10, 11 |
|---|---|---|
| 00 | $Y_1$ | $I_0, I_1, I_2, I_3$ |
| 01 | $Y_2$ | $I_4, I_5, I_6, I_7$ |
| 10 | $Y_3$ | $I_8, I_9, I_{10}, I_{11}$ |
| 11 | $Y_4$ | $I_{12}, I_{13}, I_{14}, I_{15}$ |

**Example:** $S_3S_2S_1S_0 = 1011$. Every level-1 MUX selects its input 3, so M3 outputs $I_{11}$. M5 with $S_3S_2 = 10$ selects M3, so $Y = I_{11}$, which is input number $1011_2 = 11$. Correct.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is a multiplexer tree?
   A. A single large AND-OR network
   B. Small multiplexers connected in levels to make a larger one
   C. A MUX with feedback
   D. A decoder followed by a flip-flop
   Answer: B. Level 1 selects within groups using lower select bits; the next level selects the group using higher bits. (Key point: Multiplexer tree)

2. How many 4:1 MUXes build a 16:1 MUX?
   A. Four
   B. Five
   C. Eight
   D. Three
   Answer: B. Four at level 1 (16 inputs) plus one at level 2. (Key point: MUX count)

3. Which selects drive the level-1 MUXes and the final MUX M5?
   A. S3S2 for level 1, S1S0 for M5
   B. S1S0 for level 1, S3S2 for M5
   C. S1S0 for all
   D. S3S2 for all
   Answer: B. Lower bits S1S0 choose within a group of 4; higher bits S3S2 choose the group. (Key point: Select assignment)

4. For S3S2S1S0 = 1011, which input reaches Y?
   A. I13
   B. I8
   C. I11
   D. I3
   Answer: C. Level 1 selects input 3 of each group; M5 with S3S2 = 10 picks M3, giving I11. (Key point: Worked example)

## Related in Digital Logic

- [Multiplexer tree; 1:16 DEMUX from 1:4](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademux-tree-1to16-from-1to4) — Digital Logic, chapter 4
- [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4
- [32:1 MUX tree from 4:1; implement Σ(0,1,3,8,9,13)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function) — Digital Logic, chapter 4
- [32:1 MUX from 16:1 and 2:1 MUXes](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-from-16to1) — Digital Logic, chapter 4
- [Short note: DE-MUX tree](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashort-note-demux-tree) — Digital Logic, chapter 4
- [Short note: MUX tree](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashort-note-mux-tree) — Digital Logic, chapter 4

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