---
title: "32:1 MUX from 16:1 and 2:1 MUXes"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:mux-32to1-from-16to1"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-32to1-from-16to1
site: BCT Engineering
---

# 32:1 MUX from 16:1 and 2:1 MUXes

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2068 Chaitra, 5 marks
- Video: [32*1 Multiplexer Using 16*1 Multiplexer - Combinational Logic Circuits - Application of Electronics](https://www.youtube.com/watch?v=F8L8N5B-QGA) — Ekeeda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-32to1-from-16to1
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Design a 32 to 1 multiplexer using 16 to 1 and 2 to 1 multiplexers.

## Short answer

Use two 16:1 MUXes for inputs I0–I15 and I16–I31, both with shared selects S3–S0. A 2:1 MUX with select S4 chooses between their outputs, yielding a 32:1 MUX. No extra gates needed.

## Answer

A 32:1 MUX has inputs $I_0$–$I_{31}$ and five select lines $S_4S_3S_2S_1S_0$. It is built from **two 16:1 MUXes and one 2:1 MUX** (a multiplexer tree).

#### Design

- **Level 1:** MUX-1 (16:1) takes $I_0$–$I_{15}$; MUX-2 (16:1) takes $I_{16}$–$I_{31}$. Both share the lower selects $S_3S_2S_1S_0$.
- **Level 2:** a 2:1 MUX with select $S_4$ passes MUX-1 output when $S_4 = 0$ and MUX-2 output when $S_4 = 1$.

```text
             S3 S2 S1 S0
           +-----------+
 I0-I15 -->| 16:1 MUX-1|--P--+      S4
           +-----------+     |   +------+
                             +-->|0     |
           +-----------+         | 2:1  |---> Y
 I16-I31 ->| 16:1 MUX-2|--Q----->|1     |
           +-----------+         +------+
             S3 S2 S1 S0
```

#### Output equation

$$
Y = S_4'P + S_4Q
$$

where $P = \sum_{k=0}^{15} m_k I_k$ and $Q = \sum_{k=0}^{15} m_k I_{k+16}$, with $m_k$ the minterms of $S_3S_2S_1S_0$.

| $S_4$ | $S_3S_2S_1S_0$ | Y |
|---|---|---|
| 0 | 0000 – 1111 | $I_0$ – $I_{15}$ |
| 1 | 0000 – 1111 | $I_{16}$ – $I_{31}$ |

#### Example

$S_4S_3S_2S_1S_0 = 11001$ (= 25). MUX-1 gives $I_9$ and MUX-2 gives $I_{25}$ (both select input 9). The 2:1 MUX with $S_4 = 1$ passes $Q$, so $Y = I_{25}$. Correct.

Alternative: if the 16:1 MUXes (e.g. 74150) have enable inputs, connect $S_4'$ to the enable of MUX-1 and $S_4$ to MUX-2, and OR the two outputs instead of using the 2:1 MUX.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is needed to build a 32:1 MUX from 16:1 and 2:1 MUXes?
   A. One 16:1 MUX and two 2:1 MUXes
   B. Two 16:1 MUXes and two 2:1 MUXes
   C. Four 16:1 MUXes
   D. Two 16:1 MUXes and one 2:1 MUX
   Answer: D. Two 16:1 MUXes cover the 32 inputs, and a single 2:1 MUX chooses between their outputs. (Key point: Components)

2. Which select lines go where?
   A. S3S2S1S0 to both 16:1 MUXes and S4 to the 2:1 MUX
   B. S4S3S2S1 to the 16:1 MUXes and S0 to the 2:1 MUX
   C. S4 to both 16:1 MUXes and S3 to the 2:1 MUX
   D. Different select lines to each 16:1 MUX
   Answer: A. Both 16:1 MUXes share the four lower selects and the top bit S4 picks which group (I0-I15 or I16-I31) is passed. (Key point: Select assignment)

3. For S4S3S2S1S0 = 11001, which input reaches Y?
   A. I9
   B. I25
   C. I19
   D. I24
   Answer: B. S3S2S1S0 = 1001 = 9 selects I9 in MUX-1 and I25 in MUX-2; S4 = 1 passes MUX-2, so Y = I25. (Key point: Worked example)

## Related in Digital Logic

- [16:1 MUX using 8:1 MUXes](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-16to1-from-8to1) — Digital Logic, chapter 4
- [Multiplexer tree; 16:1 MUX from 4:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-16to1-from-4to1) — Digital Logic, chapter 4
- [32:1 MUX tree from 4:1; implement Σ(0,1,3,8,9,13)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function) — Digital Logic, chapter 4
- [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4
- [8:1 MUX operation; 32:1 MUX from 8:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-32to1-tree) — Digital Logic, chapter 4
- [8:1 MUX from 4:1 and 2:1 MUXes](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-from-4to1-2to1) — Digital Logic, chapter 4

## Related in other subjects

- [Multiplexer and 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Amultiplexer-4-1) — Basic Electronics Engineering, chapter 6, asked 2×
- [Design regulator for 16 V from 25 V](https://www.bctengineer.com/question.md?key=semester_3%2Felectronics_devices_and_circuit%3Adc-regulator-design-16v-25v) — Electronics Devices and Circuit, chapter 6
- [Design LM317 regulator for 16 V from 24 V](https://www.bctengineer.com/question.md?key=semester_3%2Felectronics_devices_and_circuit%3Alm317-design-16v-24v) — Electronics Devices and Circuit, chapter 6
- [Desander design, two basins (16 m³/s)](https://www.bctengineer.com/question.md?key=semester_7%2Fhydropower_engineering%3Adesander-16cumec-two-basins) — Hydropower Engineering, chapter 5