---
title: "ΠM(0,2,6,7) using 4:1 MUX"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:mux-4to1-pom-function"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-4to1-pom-function
site: BCT Engineering
---

# ΠM(0,2,6,7) using 4:1 MUX

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2078 Kartik, 6 marks
- Video: [Implementation of Boolean function using MUX ( If Max terms and Dont care Conditions are given)](https://www.youtube.com/watch?v=R2agl_ogh-Q) — LUCKY Learning
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-4to1-pom-function
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Realize a following logic expression using a 4:1 multiplexer and standard logic gates. Y(A,B,C) = ΠM(0,2,6,7)

## Short answer

Convert ΠM(0,2,6,7) to minterms: Y = Σm(1,3,4,5). Use A, B as select lines of a 4:1 MUX. Connect data inputs: I0 = C, I1 = C, I2 = 1, I3 = 0. The MUX output yields the function.

## Answer

First convert the maxterm list to minterms. A 3-variable function has minterms 0–7; the ones not listed as maxterms are the minterms:

$$
Y = \Pi M(0,2,6,7) = \Sigma m(1,3,4,5)
$$

#### Implementation table

Use $A, B$ as select lines ($S_1 = A$, $S_0 = B$) and express each data input in terms of $C$. Input $I_j$ covers minterms $2j$ ($C = 0$) and $2j + 1$ ($C = 1$).

| | $I_0$ | $I_1$ | $I_2$ | $I_3$ |
|---|---|---|---|---|
| $C'$ | 0 | 2 | **4** | 6 |
| $C$ | **1** | **3** | **5** | 7 |
| Input | $C$ | $C$ | 1 | 0 |

- $I_0$: only minterm 1 present, so $I_0 = C$.
- $I_1$: only minterm 3, so $I_1 = C$.
- $I_2$: both 4 and 5, so $I_2 = 1$.
- $I_3$: neither 6 nor 7, so $I_3 = 0$.

#### Circuit

```text
             +--------+
  C -------->| I0     |
  C -------->| I1 4:1 |----> Y
  1 (Vcc) -->| I2 MUX |
  0 (GND) -->| I3     |
             +--------+
                S1  S0
                A   B
```

No extra gate is needed here (no $C'$ input appears).

#### Check

The MUX equation gives

$$
Y = A'B'C + A'BC + AB'(1) + AB(0) = A'C + AB'
$$

| ABC | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 |
|---|---|---|---|---|---|---|---|---|
| Y | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 |

Y is 0 exactly at 0, 2, 6, 7, which matches $\Pi M(0,2,6,7)$.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Y(A,B,C) = ΠM(0,2,6,7) equals which minterm sum?
   A. Σm(0,2,6,7)
   B. Σm(1,3,4,5)
   C. Σm(1,3,5,7)
   D. Σm(2,4,6,7)
   Answer: B. The minterms are the numbers 0-7 not listed as maxterms: 1, 3, 4, 5. (Key point: Convert maxterms to minterms)

2. With a 4:1 MUX for a 3-variable function, which variables go on the select lines?
   A. B and C, with A on data
   B. A and C, with B on data
   C. A and B, with C (or 0/1) on data
   D. All three on the selects
   Answer: C. A and B are S1 and S0, and each data input is expressed in terms of C. (Key point: Select line assignment)

3. For I0 (AB = 00) only minterm 1 (C = 1) is in the function. What is I0?
   A. C
   B. C'
   C. 1
   D. 0
   Answer: A. Y must be 1 only when C = 1, so I0 = C; I1 (only minterm 3) is also C. (Key point: I0 and I1 inputs)

4. Why is I2 = 1 and I3 = 0?
   A. Minterms 4 and 5 are both present; 6 and 7 are both absent
   B. Minterms 4 and 5 are both absent; 6 and 7 are present
   C. Only minterm 4 is present for I2
   D. Both are fixed by convention
   Answer: A. I2 covers minterms 4, 5 (both in Y) so it is 1; I3 covers 6, 7 (neither in Y) so it is 0. (Key point: Constant inputs)

## Related in Digital Logic

- [Multiplexer tree; 16:1 MUX from 4:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-16to1-from-4to1) — Digital Logic, chapter 4
- [Universal gates; positive and negative logic](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Auniversal-gates-positive-logic) — Digital Logic, chapter 2
- [Full adder using a single 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-single-4to1-mux) — Digital Logic, chapter 4
- [K-map ΠM(0,2,4,6,7,8,10,13,15) and 8:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-pom-8to1-mux) — Digital Logic, chapter 3
- [Multiplexer tree; 1:16 DEMUX from 1:4](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademux-tree-1to16-from-1to4) — Digital Logic, chapter 4
- [8:1 MUX operation; 32:1 MUX from 8:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-32to1-tree) — Digital Logic, chapter 4

## Related in other subjects

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- [Short note: Logic gates](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-logic-gates) — Basic Electrical and Electronics Engineering, chapter 3
- [K-map: x'yz + x'y'z + xyz with gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-xyz-realize-gates) — Basic Electronics Engineering, chapter 6, asked 2×