--- title: "8:1 MUX operation; 32:1 MUX from 8:1" subject: "Digital Logic" chapter: 4 key: "semester_3/digital_logic:mux-8to1-32to1-tree" source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-32to1-tree site: BCT Engineering --- # 8:1 MUX operation; 32:1 MUX from 8:1 Digital Logic · Chapter 4: Data Processing Circuits - Asked in: 2076 Chaitra, 3+3 marks - Video: [32X1 MUX using 8X1 MUX](https://www.youtube.com/watch?v=XdhygaTrwCo) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-32to1-tree - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4 ## Question Explain the operation of 8:1 multiplexer with necessary diagrams. Construct 32:1 MUX using only 8:1 MUXs. ## Short answer An 8:1 MUX selects one of 8 inputs I0–I7 using select lines S2S1S0. To build 32:1, use four 8:1 MUXes in the first level covering I0–I31 with S2S1S0. Their outputs feed a fifth 8:1 MUX with selects S4,S3 on its two lowest lines (MSB tied to 0), yielding a 32:1 MUX. ## Answer #### Operation of an 8:1 multiplexer An **8:1 multiplexer** selects one of 8 data inputs $I_0$–$I_7$ and passes it to a single output $Y$. The input is chosen by three select lines $S_2S_1S_0$ ($2^3 = 8$). $$ Y = S_2'S_1'S_0'I_0 + S_2'S_1'S_0I_1 + S_2'S_1S_0'I_2 + S_2'S_1S_0I_3 + S_2S_1'S_0'I_4 + S_2S_1'S_0I_5 + S_2S_1S_0'I_6 + S_2S_1S_0I_7 $$ | $S_2S_1S_0$ | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | |---|---|---|---|---|---|---|---|---| | Y | $I_0$ | $I_1$ | $I_2$ | $I_3$ | $I_4$ | $I_5$ | $I_6$ | $I_7$ | Internally it has eight 4-input AND gates (each gets one data input and one combination of $S_2, S_1, S_0$ or their complements) and one 8-input OR gate. Only the AND gate whose select combination is true is enabled. ```text I0..I7 ---->+---------+ | 8:1 | | MUX |-----> Y S2 S1 S0 -->+---------+ (74151) ``` #### 32:1 MUX using only 8:1 MUXes A 32:1 MUX needs 5 select lines $S_4$–$S_0$. - **Level 1:** four 8:1 MUXes (M1–M4) take $I_0$–$I_7$, $I_8$–$I_{15}$, $I_{16}$–$I_{23}$, $I_{24}$–$I_{31}$. All use $S_2S_1S_0$. - **Level 2:** a fifth 8:1 MUX (M5) selects one of the four outputs. Its select lines are $S_4$, $S_3$ on its two lower selects and its MSB select tied to 0, so only inputs $I_0$–$I_3$ of M5 are used. ```text +-----------+ I0-I7 -->[M1 8:1]-------->| I0 | I8-I15 -->[M2 8:1]-------->| I1 | I16-I23 -->[M3 8:1]-------->| I2 M5 |----> Y I24-I31 -->[M4 8:1]-------->| I3 (8:1) | 0 ---->| I4-I7 | +-----------+ M1-M4 selects: S2 S1 S0 M5 selects: 0, S4, S3 ``` Total: 5 MUXes of 8:1. Example: $S_4..S_0 = 10110$ gives M3 output $I_{16+6} = I_{22}$, and M5 with $S_4S_3 = 10$ passes M3, so $Y = I_{22}$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How many select lines does an 8:1 MUX need and why? A. 8, one per input B. 4, because 2^4 = 16 C. 3, because 2^3 = 8 D. 2, because 2^2 = 4 Answer: C. n select lines choose among 2^n inputs, so 8 inputs need 3 selects. (Key point: Select lines of 8:1 MUX) 2. What does the internal logic of an 8:1 MUX consist of? A. Eight 4-input AND gates and one 8-input OR gate B. Eight OR gates and one AND gate C. Three XOR gates D. One decoder and one NOT gate Answer: A. Each AND gate takes one data input plus a select combination; only the matching AND is enabled, and the OR combines them. (Key point: Internal structure) 3. How is a 32:1 MUX built from 8:1 MUXes? A. Four 8:1 at level 1 and one 8:1 at level 2, total 5 B. Eight 8:1 at level 1 and one at level 2, total 9 C. Two 8:1 only D. Four 8:1 in a chain with no final MUX Answer: A. Four MUXes cover 32 inputs using S2S1S0; a fifth selects one of their outputs using S4 and S3. (Key point: 32:1 tree structure) 4. How are the select lines of the final 8:1 MUX (M5) used? A. S4 S3 S2 on all three selects B. S4 and S3 on the lower selects, MSB select tied to 0 C. S2 S1 S0 again D. Only S4 is used, the others float Answer: B. Only four inputs need selecting, so S4 S3 drive the two lower selects and the top select is tied to 0. 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