---
title: "Σ(0,2,3,5,8,12,14) using 8:1 MUX; add with full adders"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:mux-8to1-add-full-adders"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-add-full-adders
site: BCT Engineering
---

# Σ(0,2,3,5,8,12,14) using 8:1 MUX; add with full adders

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2078 Bhadra, 4+3 marks
- Video: [Implement the function 𝐟(𝒂,𝒃,𝒄,𝒅)=∑(𝟎,𝟏,𝟓,𝟔,𝟕,𝟗,𝟏𝟎,𝟏𝟓)  using8:1 MUX](https://www.youtube.com/watch?v=rnPrQxPllYk) — Engg-Course-Made-Easy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-add-full-adders
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Implement the given function F = Σ(0,2,3,5,8,12,14) using only one 8:1 MUX. Add the binary numbers 1011 and 1101 by using Full adders.

## Short answer

For the MUX, use A,B,C as selects; I0=D', I1=1, I2=D, I3=0, I4=D', I5=0, I6=D', I7=D'. One inverter gives D'. For binary addition, 1011 + 1101 = 11000 (carry 1, sum 1000) using four full adders.

## Answer

#### Implementing F = Σ(0,2,3,5,8,12,14) with one 8:1 MUX

Take $A, B, C$ as select lines ($S_2S_1S_0$) and the LSB $D$ as the data variable. Each data input $I_i$ covers minterms $2i$ ($D = 0$) and $2i+1$ ($D = 1$).

| $I_i$ | ABC | Minterms ($D$=0, $D$=1) | In F? | $I_i$ |
|---|---|---|---|---|
| $I_0$ | 000 | 0, 1 | yes, no | $D'$ |
| $I_1$ | 001 | 2, 3 | yes, yes | 1 |
| $I_2$ | 010 | 4, 5 | no, yes | $D$ |
| $I_3$ | 011 | 6, 7 | no, no | 0 |
| $I_4$ | 100 | 8, 9 | yes, no | $D'$ |
| $I_5$ | 101 | 10, 11 | no, no | 0 |
| $I_6$ | 110 | 12, 13 | yes, no | $D'$ |
| $I_7$ | 111 | 14, 15 | yes, no | $D'$ |

```text
D' --> I0 +--------+
1  --> I1 |        |
D  --> I2 |  8:1   |
0  --> I3 |  MUX   |--> F
D' --> I4 |        |
0  --> I5 |        |
D' --> I6 |        |
D' --> I7 +--------+
           S2 S1 S0
           A  B  C
```

Only one NOT gate is needed for $D'$.

#### Adding 1011 and 1101 with full adders

Use a 4-bit parallel adder: four full adders FA0–FA3, with $C_0 = 0$ and each carry going to the next stage.

```text
 A3B3     A2B2     A1B1     A0B0
  1 1      0 1      1 0      1 1
 [FA3]<-C3[FA2]<-C2[FA1]<-C1[FA0]<-C0=0
  |  \     |        |        |
 C4  S3    S2       S1       S0
```

| Stage | $A_i$ | $B_i$ | $C_i$ | $S_i$ | $C_{i+1}$ |
|---|---|---|---|---|---|
| FA0 | 1 | 1 | 0 | 0 | 1 |
| FA1 | 1 | 0 | 1 | 0 | 1 |
| FA2 | 0 | 1 | 1 | 0 | 1 |
| FA3 | 1 | 1 | 1 | 1 | 1 |

**Answer:** $1011 + 1101 = 11000_2$ (carry $C_4 = 1$, sum $S_3S_2S_1S_0 = 1000$). Check: $11 + 13 = 24 = 11000_2$.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. To implement a 4-variable function on an 8:1 MUX as in this answer, what drives the select lines and the data inputs?
   A. A, B, C drive the select lines; the data inputs are 0, 1, D or D'
   B. A, B, C, D all drive the select lines
   C. D and C drive the select lines; the data inputs are A and B
   D. A, B, C drive the data inputs; D drives all select lines
   Answer: A. A 8:1 MUX has 3 select lines, so three variables select and the remaining LSB D (or its complement, 0, 1) feeds the data inputs. (Key point: Select lines and data variable)

2. For input I0 (minterms 0 and 1) the function is 1 at minterm 0 and 0 at minterm 1. What is I0?
   A. D
   B. 1
   C. D'
   D. 0
   Answer: C. When only the D=0 minterm is in F, the input is D' (it is 1 only when D = 0). (Key point: Data input rule)

3. Why is I1 connected to logic 1 for F = Σ(0,2,3,5,8,12,14)?
   A. Only minterm 3 is in F
   B. Both minterms 2 and 3 are in F, so F=1 whatever D is
   C. Neither minterm 2 nor 3 is in F
   D. Minterm 2 is in F but 3 is not
   Answer: B. I1 covers minterms 2 and 3; both are present so the output is always 1. (Key point: Constant data inputs)

4. Adding 1011 and 1101 with four full adders and C0 = 0, what is the final result?
   A. 10110
   B. 11001
   C. 01000 with no carry
   D. 11000 (carry C4 = 1, sum 1000)
   Answer: D. 11 + 13 = 24 = 11000; the stage-3 carry becomes the fifth bit. (Key point: Ripple full-adder addition)

## Related in Digital Logic

- [Σ(0,1,3,6,10,12,14) using 8×1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8x1-function-0136) — Digital Logic, chapter 4
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