---
title: "8:1 MUX from 4:1 and 2:1 MUXes"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:mux-8to1-from-4to1-2to1"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-from-4to1-2to1
site: BCT Engineering
---

# 8:1 MUX from 4:1 and 2:1 MUXes

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2079 Baisakh, 6 marks
- Video: [8:1 MUX using 4:1 MUX and 2:1 MUX [Detailed explanation with logic expression & circuit diagram]](https://www.youtube.com/watch?v=bKnl4ixZ9gE) — Simplify Tech2Learn
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-from-4to1-2to1
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Design 8:1 Multiplexer using 4:1 Multiplexer and 2:1 Multiplexer.

## Short answer

Use two 4:1 MUXes: first takes I0–I3, second takes I4–I7, both with select lines S1S0. Their outputs feed a 2:1 MUX with select S2; when S2=0 it passes the first output, when S2=1 passes the second, yielding an 8:1 multiplexer.

## Answer

An 8:1 MUX has 8 data inputs $I_0$–$I_7$ and 3 select lines $S_2S_1S_0$. It can be built as a **multiplexer tree** from two 4:1 MUXes and one 2:1 MUX.

#### Design

- **Level 1:** two 4:1 MUXes. MUX-1 takes $I_0$–$I_3$, MUX-2 takes $I_4$–$I_7$. Both use the lower select bits $S_1 S_0$.
- **Level 2:** one 2:1 MUX picks MUX-1 output (when $S_2 = 0$) or MUX-2 output (when $S_2 = 1$).

```text
           S1 S0
         +-------+
 I0 ---->|       |
 I1 ---->| 4:1   |--P--+
 I2 ---->| MUX-1 |     |    S2
 I3 ---->|       |     |  +-----+
         +-------+     +->|0    |
         +-------+        | 2:1 |---> Y
 I4 ---->|       |     +->|1    |
 I5 ---->| 4:1   |--Q--+  +-----+
 I6 ---->| MUX-2 |
 I7 ---->|       |
         +-------+
           S1 S0
```

#### Function table

| $S_2$ | $S_1$ | $S_0$ | Y |
|---|---|---|---|
| 0 | 0 | 0 | $I_0$ |
| 0 | 0 | 1 | $I_1$ |
| 0 | 1 | 0 | $I_2$ |
| 0 | 1 | 1 | $I_3$ |
| 1 | 0 | 0 | $I_4$ |
| 1 | 0 | 1 | $I_5$ |
| 1 | 1 | 0 | $I_6$ |
| 1 | 1 | 1 | $I_7$ |

#### Working

$$
P = S_1'S_0'I_0 + S_1'S_0 I_1 + S_1S_0'I_2 + S_1S_0I_3
$$
$$
Q = S_1'S_0'I_4 + S_1'S_0 I_5 + S_1S_0'I_6 + S_1S_0I_7
$$
$$
Y = S_2'P + S_2 Q
$$

Substituting gives $Y = \sum_{k=0}^{7} m_k I_k$, the 8:1 MUX equation, where $m_k$ is the minterm of $S_2S_1S_0$.

Example: $S_2S_1S_0 = 110$. Both 4:1 MUXes select their input 2, so $P = I_2$ and $Q = I_6$. The 2:1 MUX with $S_2 = 1$ passes $Q$, so $Y = I_6$. Correct.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which set of MUXes builds an 8:1 MUX in this design?
   A. One 4:1 and two 2:1
   B. Two 4:1 and one 2:1
   C. Four 2:1 and one 4:1
   D. Three 4:1
   Answer: B. Two 4:1 MUXes at level 1 handle the 8 inputs and one 2:1 MUX at level 2 picks between their outputs. (Key point: Components needed)

2. Which select lines drive the two level-1 4:1 MUXes?
   A. S2 S1
   B. S2 S0
   C. S1 S0
   D. S2 only
   Answer: C. Both 4:1 MUXes use the lower select bits S1 S0; S2 is saved for the final 2:1 MUX. (Key point: Select line assignment)

3. What does the 2:1 MUX controlled by S2 do?
   A. Passes MUX-1 output when S2 = 0 and MUX-2 output when S2 = 1
   B. Passes MUX-2 output when S2 = 0 and MUX-1 output when S2 = 1
   C. Selects between I0 and I4 only
   D. Inverts the output of MUX-1
   Answer: A. S2 = 0 selects I0-I3 through MUX-1 and S2 = 1 selects I4-I7 through MUX-2. (Key point: Role of the 2:1 MUX)

4. For S2S1S0 = 110, which input appears at Y?
   A. I2
   B. I3
   C. I7
   D. I6
   Answer: D. Both 4:1 MUXes select their input 2, so P = I2 and Q = I6; S2 = 1 passes Q, giving Y = I6. (Key point: Worked example)

## Related in Digital Logic

- [32:1 MUX from 16:1 and 2:1 MUXes](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-from-16to1) — Digital Logic, chapter 4
- [Multiplexer tree; 16:1 MUX from 4:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-16to1-from-4to1) — Digital Logic, chapter 4
- [16:1 MUX using 8:1 MUXes](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-16to1-from-8to1) — Digital Logic, chapter 4
- [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4
- [8:1 MUX operation; 32:1 MUX from 8:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-32to1-tree) — Digital Logic, chapter 4
- [32:1 MUX tree from 4:1; implement Σ(0,1,3,8,9,13)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function) — Digital Logic, chapter 4

## Related in other subjects

- [Multiplexer and 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Amultiplexer-4-1) — Basic Electronics Engineering, chapter 6, asked 2×