---
title: "Σm(2,4,5,7,10,14) using a single 8:1 MUX"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:mux-8to1-function-2457"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-function-2457
site: BCT Engineering
---

# Σm(2,4,5,7,10,14) using a single 8:1 MUX

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2079 Bhadra, 5 marks
- Video: [Implementation of Boolean Function using Multiplexers || 8:1 || 4:1 || implementing boolean function](https://www.youtube.com/watch?v=AwZCNhxgKFY) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-function-2457
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Implement the following Boolean function using a single 8:1 multiplexer. F(A,B,C,D) = Σm(2,4,5,7,10,14).

## Short answer

Connect A, B, C to the 8:1 MUX select lines. Set data inputs: I0=0, I1=D', I2=1, I3=D, I4=0, I5=D', I6=0, I7=D'. The output F implements Σm(2,4,5,7,10,14) with an inverter for D'.

## Answer

Use $A, B, C$ as the select lines $S_2S_1S_0$ of the 8:1 MUX and feed each data input with $0$, $1$, $D$ or $D'$.

#### Implementation table

Each data input $I_j$ corresponds to $ABC = j$ and covers minterms $2j$ ($D=0$) and $2j+1$ ($D=1$). Required minterms: 2, 4, 5, 7, 10, 14.

| $I_j$ | ABC | Minterms (D=0, D=1) | In F? | $I_j$ |
|---|---|---|---|---|
| $I_0$ | 000 | 0, 1 | no, no | 0 |
| $I_1$ | 001 | 2, 3 | yes, no | $D'$ |
| $I_2$ | 010 | 4, 5 | yes, yes | 1 |
| $I_3$ | 011 | 6, 7 | no, yes | $D$ |
| $I_4$ | 100 | 8, 9 | no, no | 0 |
| $I_5$ | 101 | 10, 11 | yes, no | $D'$ |
| $I_6$ | 110 | 12, 13 | no, no | 0 |
| $I_7$ | 111 | 14, 15 | yes, no | $D'$ |

The same result in the usual two-row form:

| | $I_0$ | $I_1$ | $I_2$ | $I_3$ | $I_4$ | $I_5$ | $I_6$ | $I_7$ |
|---|---|---|---|---|---|---|---|---|
| $D'$ | 0 | **2** | **4** | 6 | 8 | **10** | 12 | **14** |
| $D$ | 1 | 3 | **5** | **7** | 9 | 11 | 13 | 15 |
| Input | 0 | $D'$ | 1 | $D$ | 0 | $D'$ | 0 | $D'$ |

#### Circuit

```text
             +--------+
  0 -------->| I0     |
  D --[NOT]->| I1     |
  1 -------->| I2     |
  D -------->| I3 8:1 |----> F
  0 -------->| I4 MUX |
  D' ------->| I5     |
  0 -------->| I6     |
  D' ------->| I7     |
             +--------+
               S2 S1 S0
               A  B  C
```

Only one inverter is needed besides the MUX.

**Check:** $ABCD = 1010$ (minterm 10): select $101$ picks $I_5 = D' = 1$, so $F = 1$. $ABCD = 1011$ (minterm 11): $I_5 = D' = 0$, so $F = 0$. Correct.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. To implement a 4-variable function with a single 8:1 MUX, what is connected to the select lines?
   A. B, C, D with A on the data side
   B. A, B, C with D (or its complement, 0, 1) on the data side
   C. Any three minterms
   D. A, B, C, D together
   Answer: B. A, B, C are the three selects S2S1S0, and each data input is 0, 1, D or D'. (Key point: Select line choice)

2. For I1 (ABC = 001), minterm 2 (D = 0) is in F but minterm 3 (D = 1) is not. What is I1?
   A. D
   B. 1
   C. D'
   D. 0
   Answer: C. I1 must be 1 when D = 0 and 0 when D = 1, which is D'. (Key point: Data input rule)

3. Why is I2 connected to logic 1?
   A. Neither minterm 4 nor 5 is in F
   B. Both minterms 4 and 5 are in F
   C. Only minterm 5 is in F
   D. Minterm 6 is in F
   Answer: B. I2 covers minterms 4 (D=0) and 5 (D=1); both are in F, so the input is constant 1. (Key point: Input with both minterms)

4. Which is the correct set of data inputs I0 to I7 for F = Σm(2,4,5,7,10,14)?
   A. 0, D', 1, D, 0, D', 0, D'
   B. 0, D, 1, D', 0, D, 0, D
   C. 1, D', 0, D, 1, D', 1, D'
   D. 0, D', 1, D', 0, D', 0, D
   Answer: A. From the table the inputs are 0, D', 1, D, 0, D', 0, D', needing only one inverter. (Key point: Resulting connections)

## Related in Digital Logic

- [Σ(0,1,3,6,10,12,14) using 8×1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8x1-function-0136) — Digital Logic, chapter 4
- [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4
- [32:1 MUX tree from 4:1; implement Σ(0,1,3,8,9,13)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function) — Digital Logic, chapter 4
- [Σ(0,2,3,5,8,12,14) using 8:1 MUX; add with full adders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-add-full-adders) — Digital Logic, chapter 4
- [Multiplexer tree; 16:1 MUX from 4:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-16to1-from-4to1) — Digital Logic, chapter 4
- [K-map ΠM(0,2,4,6,7,8,10,13,15) and 8:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-pom-8to1-mux) — Digital Logic, chapter 3

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