--- title: "F(W,X,Y,Z) using 8:1 MUX" subject: "Digital Logic" chapter: 4 key: "semester_3/digital_logic:mux-8to1-function-wxyz" source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-function-wxyz site: BCT Engineering --- # F(W,X,Y,Z) using 8:1 MUX Digital Logic · Chapter 4: Data Processing Circuits - Asked in: 2070 Chaitra, 4 marks - Video: [Design of MUX: Realize the Boolean function f(w, x, y, z) ="Σ" (0, 1, 5, 6, 7, 9, 12, 15)](https://www.youtube.com/watch?v=GfooDsY-7rc) — Engg-Course-Made-Easy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8to1-function-wxyz - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4 ## Question Realize the logic circuit of the following using 8:1 MUX. F(W,X,Y,Z) = Σm(1,2,5,7,8,10,12,13,15) ## Short answer Use an 8:1 MUX with W,X,Y as selects. Data inputs: I0=Z, I1=Z', I2=Z, I3=Z, I4=Z', I5=Z', I6=1, I7=Z. One NOT gate provides Z'. The output implements the given minterms. ## Answer Use $W, X, Y$ as the select lines $S_2S_1S_0$ of the 8:1 MUX and connect $Z$, $Z'$, 0 or 1 to the data inputs. Input $I_j$ covers minterms $2j$ ($Z = 0$) and $2j+1$ ($Z = 1$). Required minterms: 1, 2, 5, 7, 8, 10, 12, 13, 15. | | $I_0$ | $I_1$ | $I_2$ | $I_3$ | $I_4$ | $I_5$ | $I_6$ | $I_7$ | |---|---|---|---|---|---|---|---|---| | $Z'$ | 0 | **2** | 4 | 6 | **8** | **10** | **12** | 14 | | $Z$ | **1** | 3 | **5** | **7** | 9 | 11 | **13** | **15** | | Input | $Z$ | $Z'$ | $Z$ | $Z$ | $Z'$ | $Z'$ | 1 | $Z$ | ```text +--------+ Z -------->| I0 | Z' ------->| I1 | Z -------->| I2 | Z -------->| I3 8:1 |----> F Z' ------->| I4 MUX | Z' ------->| I5 | 1 -------->| I6 | Z -------->| I7 | +--------+ W X Y (Z' from one NOT gate) ``` **Check:** $WXYZ = 1100$ (12): select 110 → $I_6 = 1$, so $F = 1$. $WXYZ = 1001$ (9): select 100 → $I_4 = Z' = 0$, so $F = 0$ (9 is not a minterm). Correct. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In realising F(W,X,Y,Z) with an 8:1 MUX, what is connected to the select lines and why? A. W, X, Y to the selects, since each data input then covers two minterms differing in Z B. Z, Y, X to the selects, since Z is the MSB C. All four variables to the selects D. W, X, Y to the data inputs Answer: A. Input Ij covers minterms 2j and 2j+1, which differ only in Z, so Z, Z', 0 or 1 is applied to the data input. (Key point: Select lines) 2. F = Σm(1,2,5,7,8,10,12,13,15). What is connected to I6, which covers minterms 12 and 13? A. Z B. 1 C. Z' D. 0 Answer: B. Both 12 and 13 are minterms of F, so the output is 1 whatever Z is, and I6 is tied to 1. (Key point: Data input I6) 3. What is connected to I1, covering minterms 2 and 3? A. Z B. 1 C. Z' D. 0 Answer: C. Minterm 2 (Z=0) is in F and minterm 3 (Z=1) is not, so I1 = Z'. (Key point: Data input I1) ## Related in Digital Logic - [Σ(0,2,3,6,7,8,12,13,15) using 8×1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8x1-function-0236) — Digital Logic, chapter 4 - [K-map Σ(0,1,4,8,10,11,12)+d, realize circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-realize-circuit-01248) — Digital Logic, chapter 3, asked 2× - [K-map ΠM(0,2,4,6,7,8,10,13,15) and 8:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-pom-8to1-mux) — Digital Logic, chapter 3 - [K-map Σ(0,2,3,4,7,8,10,13)+d, logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-logic-circuit-0234) — Digital Logic, chapter 3 - [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4 - [K-map Σm(7,9,12,13,14,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-sum-7-9-12) — Digital Logic, chapter 3 ## Related in other subjects - [Q and center frequency; realize −2000/(s²+500s+10⁶)](https://www.bctengineer.com/question.md?key=semester_5%2Ffilter_design%3Atow-thomas-q-center-frequency-realize) — Filter Design, chapter 6 - [Tow-Thomas LPF derivation; realize −2000/(s²+500s+10⁶)](https://www.bctengineer.com/question.md?key=semester_5%2Ffilter_design%3Atow-thomas-realize-2000-tf) — Filter Design, chapter 6 - [Hill road earthwork, chainage 12-15](https://www.bctengineer.com/question.md?key=semester_7%2Festimating_and_costing%3Ahill-road-q-chain-12-15) — Estimating and Costing, chapter 6 - [Standard error; population 12,19,13,16](https://www.bctengineer.com/question.md?key=semester_5%2Fprobability_and_statistics%3Astandard-error-population-12-19-13) — Probability and Statistics, chapter 4