--- title: "Σ(0,1,3,6,10,12,14) using 8×1 MUX" subject: "Digital Logic" chapter: 4 key: "semester_3/digital_logic:mux-8x1-function-0136" source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8x1-function-0136 site: BCT Engineering --- # Σ(0,1,3,6,10,12,14) using 8×1 MUX Digital Logic · Chapter 4: Data Processing Circuits - Asked in: 2078 Kartik, 4 marks - Video: [Implement given Boolean Function using mux | Boolean function using 8:1 MUX](https://www.youtube.com/watch?v=qOJXifXkQ0w) — Explore Electronics - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8x1-function-0136 - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4 ## Question Implement the given function F = Σ(0,1,3,6,10,12,14) using 8×1 MUX only. ## Short answer Connect A,B,C to select lines. Inputs: I0=1, I1=D, I2=0, I3=D', I4=0, I5=D', I6=D', I7=D'. One inverter provides D'. ## Answer Use $A, B, C$ as the select lines ($S_2 S_1 S_0$) and the LSB $D$ as the data variable. Data input $I_i$ covers minterm $2i$ (when $D=0$) and $2i+1$ (when $D=1$). **Implementation table** (F = Σ(0,1,3,6,10,12,14)): | | $I_0$ | $I_1$ | $I_2$ | $I_3$ | $I_4$ | $I_5$ | $I_6$ | $I_7$ | |---|---|---|---|---|---|---|---|---| | $D'$ row | **0** | 2 | 4 | **6** | 8 | **10** | **12** | **14** | | $D$ row | **1** | **3** | 5 | 7 | 9 | 11 | 13 | 15 | | Input | 1 | $D$ | 0 | $D'$ | 0 | $D'$ | $D'$ | $D'$ | (Bold = minterm present in F.) Rules: both entries present gives 1, none gives 0, only the $D'$ row gives $D'$, only the $D$ row gives $D$. ```text 1 --> I0 +--------+ D --> I1 | | 0 --> I2 | 8x1 | D' --> I3 | MUX |--> F 0 --> I4 | | D' --> I5 | | D' --> I6 | | D' --> I7 +--------+ S2 S1 S0 A B C ``` Inputs 1 and 0 are tied to $V_{CC}$ and ground; one inverter gives $D'$. **Check:** $ABCD = 1100$ (minterm 12) selects $I_6 = D' = 1$, so $F = 1$; $ABCD = 0101$ (minterm 5) selects $I_2 = 0$, so $F = 0$. Both agree with the given function. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In this answer which variables are on the select lines S2 S1 S0 of the 8x1 MUX? A. A, B, C (D is the data variable) B. B, C, D C. A, C, D D. D, C, B Answer: A. Three select lines take A, B, C and the LSB D is used to form the data inputs. (Key point: Select assignment) 2. For F = Σ(0,1,3,6,10,12,14), I0 covers minterms 0 and 1, both in F. What is I0? A. D B. D' C. 1 D. 0 Answer: C. Both minterms are present, so the output is 1 regardless of D. (Key point: Reading I0) 3. I1 covers minterms 2 and 3; only 3 (D=1) is in F. What is I1? A. D' B. D C. 1 D. 0 Answer: B. Only the D=1 row is present, so the input is D. (Key point: Reading I1) 4. How many extra gates are needed for the circuit? A. No gates at all B. One inverter for D and one for D' C. Three AND gates D. One inverter to make D' Answer: D. Inputs 1 and 0 are tied to Vcc and ground, and a single NOT gate supplies D'. (Key point: Number of inverters) ## Related in Digital Logic - [Σ(0,2,3,5,8,12,14) using 8:1 MUX; add with full adders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-add-full-adders) — Digital Logic, chapter 4 - [K-map Σm(7,9,12,13,14,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-sum-7-9-12) — Digital Logic, chapter 3 - [Σm(2,4,5,7,10,14) using a single 8:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-function-2457) — Digital Logic, chapter 4 - [K-map Σm(0,1,2,4,7,8,9,10,12,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-only-01247) — Digital Logic, chapter 3 - [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4 - [K-map Σ(0,1,4,8,10,11,12)+d, NAND-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-only-01248) — Digital Logic, chapter 3 ## Related in other subjects - [Class C pool for 10, 12, 8, 14](https://www.bctengineer.com/question.md?key=semester_7%2Fcomputer_networks_and_security%3Asubnetting-class-c-four-depts) — Computer Networks and Security, chapter 4, asked 2× - [T/F: tower height function of voltage only](https://www.bctengineer.com/question.md?key=semester_8%2Ftransmission_and_distribution_system_design%3Atf-tower-height-voltage-only) — Transmission and Distribution System Design, chapter 4, asked 2× - [ERR with MARR 12% and reinvestment 14%](https://www.bctengineer.com/question.md?key=semester_6%2Fengineering_economics%3Aerr-reinvestment-14) — Engineering Economics, chapter 3 - [Signal timing: roads A 14.4 m and B 12 m](https://www.bctengineer.com/question.md?key=semester_7%2Ftransportation_engineering_ii%3Asignal-pedestrian-road-a-14-4m) — Transportation Engineering II, chapter 1