---
title: "Σ(0,2,3,6,7,8,12,13,15) using 8×1 MUX"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:mux-8x1-function-0236"
source: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8x1-function-0236
site: BCT Engineering
---

# Σ(0,2,3,6,7,8,12,13,15) using 8×1 MUX

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2075 Chaitra, 5 marks
- Video: [Implement given Boolean Function using mux | Boolean function using 8:1 MUX](https://www.youtube.com/watch?v=qOJXifXkQ0w) — Explore Electronics
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/mux-8x1-function-0236
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Implement the following function using 8×1 MUX. F(A,B,C,D) = Σ(0,2,3,6,7,8,12,13,15)

## Short answer

Use A,B,C as select lines and D as data input. Determine each MUX input Ii from the minterms: I0=D', I1=1, I2=0, I3=1, I4=D', I5=0, I6=1, I7=D. Connect accordingly with one inverter for D'.

## Answer

Use $A, B, C$ as select lines ($S_2S_1S_0$) and $D$ (LSB) as the data variable. Input $I_i$ corresponds to minterms $2i$ (with $D=0$) and $2i+1$ (with $D=1$).

**Implementation table** for $F = \Sigma(0,2,3,6,7,8,12,13,15)$ (bold = minterm in F):

| | $I_0$ | $I_1$ | $I_2$ | $I_3$ | $I_4$ | $I_5$ | $I_6$ | $I_7$ |
|---|---|---|---|---|---|---|---|---|
| $D'$ row | **0** | **2** | 4 | **6** | **8** | 10 | **12** | 14 |
| $D$ row | 1 | **3** | 5 | **7** | 9 | 11 | **13** | **15** |
| Input | $D'$ | 1 | 0 | 1 | $D'$ | 0 | 1 | $D$ |

Rule: both entries bold gives 1, neither gives 0, only the upper ($D'$) row gives $D'$, and only the lower ($D$) row gives $D$.

**Circuit:**

```text
D' --> I0 +--------+
1  --> I1 |        |
0  --> I2 |  8x1   |
1  --> I3 |  MUX   |--> F
D' --> I4 |        |
0  --> I5 |        |
1  --> I6 |        |
D  --> I7 +--------+
           S2 S1 S0
           A  B  C
```

Logic 1 is tied to $V_{CC}$, logic 0 to ground, and a NOT gate gives $D'$.

**Verification:**

| ABCD | Minterm | Selected input | F |
|---|---|---|---|
| 0000 | 0 | $I_0 = D' = 1$ | 1 |
| 0001 | 1 | $I_0 = D' = 0$ | 0 |
| 1101 | 13 | $I_6 = 1$ | 1 |
| 1110 | 14 | $I_7 = D = 0$ | 0 |
| 1111 | 15 | $I_7 = D = 1$ | 1 |

All agree with the given minterm list, so the function is realized with one 8×1 MUX and one inverter.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. For F = Σ(0,2,3,6,7,8,12,13,15), I1 covers minterms 2 and 3, both in F. What is I1?
   A. 1
   B. D
   C. D'
   D. 0
   Answer: A. Both rows present gives constant 1. (Key point: Reading I1)

2. I0 covers 0 and 1; only 0 is in F. What is I0?
   A. D
   B. D'
   C. 1
   D. 0
   Answer: B. Only the D=0 row is in F, so the input is D'. (Key point: Reading I0)

3. I7 covers 14 and 15; only 15 is in F. What is I7?
   A. D'
   B. 0
   C. D
   D. 1
   Answer: C. Only the D=1 row is present, giving D. (Key point: Reading I7)

4. What is required for this realisation?
   A. Two MUXes
   B. One MUX and three AND gates
   C. A 16x1 MUX
   D. One 8x1 MUX and one inverter
   Answer: D. Only D' is needed, and constants come from Vcc and ground. (Key point: Resources)

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