--- title: "n-bit full adder block diagram" subject: "Digital Logic" chapter: 5 key: "semester_3/digital_logic:n-bit-full-adder" source: https://www.bctengineer.com/q/semester_3/digital_logic/n-bit-full-adder site: BCT Engineering --- # n-bit full adder block diagram Digital Logic · Chapter 5: Arithmetic Circuits - Asked in: 2068 Chaitra, 8 marks - Video: [N Bit Parallel Adder 4 Bit Parallel Adder](https://www.youtube.com/watch?v=DwoM9_Qq3r4) — TutorialsPoint - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/n-bit-full-adder - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5 ## Question Draw the block diagram of n-bit full adder and explain its operation. ## Short answer N full adders in cascade, each computing S_i = A_i⊕B_i⊕C_i and C_{i+1} = A_iB_i + C_i(A_i⊕B_i). All operand bits applied simultaneously; carry ripples from LSB to MSB, producing (n+1)-bit result C_n S_{n-1}...S0. Worst-case delay is n times the carry propagation delay of a single stage. ## Answer An **n-bit full adder (n-bit parallel adder)** adds two n-bit binary numbers $A = A_{n-1}\dots A_1A_0$ and $B = B_{n-1}\dots B_1B_0$ plus an input carry $C_0$. It is made by cascading $n$ one-bit full adders: the carry output of each stage is connected to the carry input of the next higher stage. #### Block diagram ```text A(n-1)B(n-1) A2 B2 A1 B1 A0 B0 | | | | | | | | +--------+ +------+ +------+ +------+ | FA n-1 |<...| FA2 |<--| FA1 |<--| FA0 |<-C0 +--------+ C3 +------+ C2+------+ C1+------+ | | | | | Cn S(n-1) S2 S1 S0 ``` #### One stage (full adder) $$ S_i = A_i \oplus B_i \oplus C_i $$ $$ C_{i+1} = A_iB_i + C_i(A_i \oplus B_i) $$ | $A_i$ | $B_i$ | $C_i$ | $S_i$ | $C_{i+1}$ | |---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 | #### Operation 1. All $2n$ input bits are applied at the same time (parallel inputs). $C_0$ is 0 for plain addition (it is set to 1 for 2's complement subtraction). 2. FA0 adds $A_0$, $B_0$, $C_0$ and gives $S_0$ and $C_1$. 3. $C_1$ enters FA1, which produces $S_1$ and $C_2$; the carry **ripples** stage by stage to the left. 4. The last stage gives $S_{n-1}$ and the final carry $C_n$. The result is the $(n+1)$-bit number $C_nS_{n-1}\dots S_0$. **Example (n = 4):** $A = 1001\ (9)$, $B = 0111\ (7)$, $C_0 = 0$: | Stage | $A_i$ | $B_i$ | $C_i$ | $S_i$ | $C_{i+1}$ | |---|---|---|---|---|---| | 0 | 1 | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | 0 | 1 | | 2 | 0 | 1 | 1 | 0 | 1 | | 3 | 1 | 0 | 1 | 0 | 1 | Result $= 1\,0000 = 16$. #### Timing and expansion - Each stage must wait for the carry from the previous stage, so the worst-case delay is about $n \cdot t_c$ (where $t_c$ is the carry delay of one full adder). This **carry propagation delay** grows with $n$. - Larger adders are built by cascading 4-bit adder ICs (7483/74283): $C_4$ of one IC goes to $C_0$ of the next. - For high speed, the carry chain is replaced by a **carry look-ahead** generator, which forms all carries directly from $G_i = A_iB_i$ and $P_i = A_i \oplus B_i$. - With XOR gates on the B inputs and $C_0 = 1$, the same circuit works as an n-bit subtractor (adder/subtractor). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is an n-bit full adder constructed? A. By cascading n one-bit full adders B. With one full adder used n times in a loop C. With n half adders only D. With a n:1 MUX Answer: A. Carry of each stage feeds the next. (Key point: Construction) 2. Which equation gives the carry out of stage i? A. Ci+1 = Ai xor Bi xor Ci B. Ci+1 = AiBi + Ci(Ai xor Bi) C. Ci+1 = Ai + Bi D. Ci+1 = Ci Answer: B. Carry is generated by AiBi or propagated when Ai xor Bi = 1. (Key point: Carry equation) 3. How does worst-case delay change with n? A. Constant B. Grows as 2^n C. Grows linearly, about n x tc D. Decreases Answer: C. Carry must ripple through all stages. (Key point: Delay) 4. How can the same circuit subtract? A. Set C0 = 0 and swap A and B B. Use only half adders C. Invert the sum D. XOR on B inputs and C0 = 1 Answer: D. This forms A + 2's complement of B. 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