---
title: "Priority encoder and octal priority encoder"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:octal-priority-encoder"
source: https://www.bctengineer.com/q/semester_3/digital_logic/octal-priority-encoder
site: BCT Engineering
---

# Priority encoder and octal priority encoder

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2078 Kartik, 2+6 marks; 2069 Chaitra, 2+4 marks (asked 2 times)
- Video: [Priority Encoder](https://www.youtube.com/watch?v=kEj-m3YuGa4) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/octal-priority-encoder
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

What is a priority encoder? Design an octal priority encoder.

## Short answer

A priority encoder outputs the code of the highest active input and a valid bit V. For an octal encoder with D7 highest, A2 = D4+D5+D6+D7, A1 = D6+D7 + D3·D4'·D5' + D2·D4'·D5', A0 = D7 + D5·D6' + D3·D4'·D6' + D1·D2'·D4'·D6', V = OR of all inputs.

## Answer

A **priority encoder** is an encoder that, when more than one input is active at the same time, outputs the code of the input with the **highest priority** and ignores the others. It also has a **valid output** V that is 1 when at least one input is active, to separate "input $D_0$ active" from "no input active" (both give code 000).

#### Octal (8-to-3) priority encoder

Inputs $D_0$–$D_7$ (active high), $D_7$ has the highest priority. Outputs $A_2A_1A_0$ (binary code) and V. X = don't care.

| $D_7$ | $D_6$ | $D_5$ | $D_4$ | $D_3$ | $D_2$ | $D_1$ | $D_0$ | $A_2$ | $A_1$ | $A_0$ | V |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | X | X | X | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | X | 0 | 0 | 1 | 1 |
| 0 | 0 | 0 | 0 | 0 | 1 | X | X | 0 | 1 | 0 | 1 |
| 0 | 0 | 0 | 0 | 1 | X | X | X | 0 | 1 | 1 | 1 |
| 0 | 0 | 0 | 1 | X | X | X | X | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | X | X | X | X | X | 1 | 0 | 1 | 1 |
| 0 | 1 | X | X | X | X | X | X | 1 | 1 | 0 | 1 |
| 1 | X | X | X | X | X | X | X | 1 | 1 | 1 | 1 |

#### Output equations

Each output is 1 for the rows where the highest active input has that bit set. For example, $A_0 = 1$ for highest input 7, 5, 3 or 1. Input 5 counts only if 6 and 7 are 0, and so on. After simplification (a term like $\overline{D_7}D_6$ reduces to $D_6$ because $D_7 + \overline{D_7}D_6 = D_7 + D_6$):

$$
\begin{aligned} A_2 &= D_4 + D_5 + D_6 + D_7 \\ A_1 &= D_7 + D_6 + D_3\overline{D_4}\,\overline{D_5} + D_2\overline{D_4}\,\overline{D_5} \\ A_0 &= D_7 + D_5\overline{D_6} + D_3\overline{D_4}\,\overline{D_6} + D_1\overline{D_2}\,\overline{D_4}\,\overline{D_6} \\ V &= D_0 + D_1 + D_2 + D_3 + D_4 + D_5 + D_6 + D_7 \end{aligned}
$$

#### Logic diagram

```text
D4,D5,D6,D7 ─────────────────[OR]── A2

D7 ─────────────────────────┐
D6 ─────────────────────────┤
D3,D4',D5' ──[AND]──────────┼[OR]── A1
D2,D4',D5' ──[AND]──────────┘

D7 ─────────────────────────┐
D5,D6' ──────[AND]──────────┤
D3,D4',D6' ──[AND]──────────┼[OR]── A0
D1,D2',D4',D6' ─[AND]───────┘

D0 ... D7 ───────────────────[OR]── V
```

Complements $\overline{D_2}, \overline{D_4}, \overline{D_5}, \overline{D_6}$ come from NOT gates.

**Example:** $D_6 = D_3 = D_1 = 1$, others 0. Then $A_2 = 1$, $A_1 = D_6 = 1$, $A_0 = 0$ (since $\overline{D_6} = 0$ blocks every term except $D_7$). Output = 110 = 6, the highest-priority active input, and V = 1. The IC 74148 is a standard 8-to-3 priority encoder (with active-low inputs and outputs).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does a priority encoder do when several inputs are active?
   A. Outputs the OR of all codes
   B. Outputs the code of the highest-priority active input
   C. Outputs an error
   D. Outputs the lowest input code
   Answer: B. It encodes only the highest-priority active input and ignores the others. (Key point: Priority encoder definition)

2. Why is the valid output V needed?
   A. To distinguish D0 active from no input active, both giving 000
   B. To raise priority
   C. To enable the outputs
   D. To invert the code
   Answer: A. V = 1 when at least one input is active, so code 000 can be told apart for D0 and no input. (Key point: Valid output)

3. What is A2 for the octal priority encoder?
   A. D4 + D5 + D6 + D7
   B. D1 + D3 + D5 + D7
   C. D2 + D3 + D6 + D7
   D. D7 only
   Answer: A. A2 = 1 whenever the highest active input is 4, 5, 6 or 7, and the lower-priority terms simplify away. (Key point: A2 equation)

4. With D6 = D3 = D1 = 1 and the rest 0, what is A2A1A0?
   A. 111
   B. 110
   C. 011
   D. 001
   Answer: B. D6 is the highest active input, so the output is 110. (Key point: Priority example)

## Close variants set in other exams

- [Octal priority encoder design](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-priority-encoder-design) — Digital Logic, chapter 4, asked 3×

## Related in Digital Logic

- [Octal-to-binary encoder; A+B'C canonical form](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-binary-encoder-canonical) — Digital Logic, chapter 4
- [4:2 priority encoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-4to2) — Digital Logic, chapter 4
- [Priority encoder; "e" and "f" segments](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-e-f-segments) — Digital Logic, chapter 4
- [Priority encoder; 4-to-2 priority encoder logic](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-4to2-expressions) — Digital Logic, chapter 4
- [Encoder and octal-to-binary (8-to-3) encoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-to-binary-encoder) — Digital Logic, chapter 4, asked 2×