---
title: "Octal priority encoder design"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:octal-priority-encoder-design"
source: https://www.bctengineer.com/q/semester_3/digital_logic/octal-priority-encoder-design
site: BCT Engineering
---

# Octal priority encoder design

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2075 Chaitra, 7 marks
- Video: [Q. 4.32: Specify the truth table of an octal-to-binary priority encoder. Provide an output V to](https://www.youtube.com/watch?v=JUqLp6p137k) — Dr. Dhiman (Learn the art of problem solving) 
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/octal-priority-encoder-design
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Design the operation of octal priority encoder with neat diagram.

## Short answer

The encoder outputs 3-bit binary code of the highest active input (D7 highest priority) and a valid bit V = D0+...+D7. Y2 = D4+D5+D6+D7; Y1 = D7+D6+D5'D4'D3+D5'D4'D2; Y0 = D7+D6'D5+D6'D4'D3+D6'D4'D2'D1. Uses AND and OR gates with inverters.

## Answer

An **octal (8-to-3) priority encoder** has eight inputs $D_0$–$D_7$ and three outputs $Y_2Y_1Y_0$ giving the binary code of the **highest-numbered active input** ($D_7$ = highest priority). A valid output $V$ is 1 when any input is active. The 74148 is a common IC (active-low).

#### Truth table (X = don't care)

| $D_7$ | $D_6$ | $D_5$ | $D_4$ | $D_3$ | $D_2$ | $D_1$ | $D_0$ | $Y_2$ | $Y_1$ | $Y_0$ | V |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | X | X | X | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | X | 0 | 0 | 1 | 1 |
| 0 | 0 | 0 | 0 | 0 | 1 | X | X | 0 | 1 | 0 | 1 |
| 0 | 0 | 0 | 0 | 1 | X | X | X | 0 | 1 | 1 | 1 |
| 0 | 0 | 0 | 1 | X | X | X | X | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | X | X | X | X | X | 1 | 0 | 1 | 1 |
| 0 | 1 | X | X | X | X | X | X | 1 | 1 | 0 | 1 |
| 1 | X | X | X | X | X | X | X | 1 | 1 | 1 | 1 |

#### Output equations

Write each output as the OR of the rows where it is 1; each row requires all higher inputs to be 0, and redundant conditions are dropped.

- $Y_2 = 1$ for highest input 4, 5, 6 or 7:
$$
Y_2 = D_4 + D_5 + D_6 + D_7
$$
- $Y_1 = 1$ for highest input 2, 3, 6 or 7. Inputs 2 and 3 count only if $D_4 = D_5 = 0$ (if $D_6$ or $D_7$ is 1, $Y_1$ is 1 anyway):
$$
Y_1 = D_7 + D_6 + D_5'D_4'D_3 + D_5'D_4'D_2
$$
- $Y_0 = 1$ for highest input 1, 3, 5 or 7:
$$
Y_0 = D_7 + D_6'D_5 + D_6'D_4'D_3 + D_6'D_4'D_2'D_1
$$
- Valid bit:
$$
V = D_0 + D_1 + \dots + D_7
$$

#### Logic diagram

```text
 D4,D5,D6,D7 ----------------------[OR 4]--- Y2

 D7 ---------------------------+
 D6 ---------------------------+
 D5',D4',D3 ---[AND 3]---------+--[OR 4]--- Y1
 D5',D4',D2 ---[AND 3]---------+

 D7 ---------------------------+
 D6',D5 -------[AND 2]---------+
 D6',D4',D3 ---[AND 3]---------+--[OR 4]--- Y0
 D6',D4',D2',D1 [AND 4]--------+

 D0 ... D7 ------------------------[OR 8]--- V
```

Inverters provide $D_2', D_4', D_5', D_6'$.

#### Operation

When several keys or interrupt lines are active together, only the highest one is encoded. Example: $D_6 = D_3 = D_1 = 1$, others 0. Then $Y_2 = 1$, $Y_1 = 1$ (from $D_6$), $Y_0 = 0$ (since $D_6' = 0$ blocks all $Y_0$ terms and $D_7 = 0$). Output $110 = 6$ and $V = 1$. All 255 non-zero input patterns were checked against these equations.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. If D6, D3 and D1 are all 1, what does the octal priority encoder output?
   A. 001
   B. 011
   C. 110
   D. 111
   Answer: C. The highest-numbered active input is D6, so the output is 110 with V = 1. (Key point: Priority rule)

2. Why is Y2 = D4 + D5 + D6 + D7?
   A. Y2 is 1 whenever the highest active input is 4, 5, 6 or 7 (code has MSB 1)
   B. Y2 is 1 only when D7 is active
   C. Y2 is 1 for inputs 0 to 3
   D. It needs complemented higher inputs for each term
   Answer: A. Any input from 4 to 7 has MSB 1, and a higher input still gives MSB 1, so no complements are needed. (Key point: Y2 equation)

3. Why does the term D5'D4'D3 appear in Y1?
   A. D3 counts only if D5 and D4 are 0, otherwise a higher input decides
   B. To make Y1 zero when D3 is active
   C. Because D5 and D4 are the lowest priority
   D. To generate the valid bit
   Answer: A. If D4 or D5 is active the highest input is above 3 and its code gives Y1 = 0, so D3 counts only when both are 0 (D6, D7 are covered by their own terms). (Key point: Blocking by higher inputs)

4. What does V = D0 + D1 + ... + D7 indicate?
   A. The code is odd
   B. At least one input is active
   C. More than one input is active
   D. D7 is active
   Answer: B. V = 1 whenever any input is active, so outputs 000 from D0 can be told from no input. (Key point: Valid bit)

## Close variants set in other exams

- [Priority encoder and octal priority encoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-priority-encoder) — Digital Logic, chapter 4, asked 3×

## Related in Digital Logic

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- [4:2 priority encoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-4to2) — Digital Logic, chapter 4
- [Priority encoder; "e" and "f" segments](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-e-f-segments) — Digital Logic, chapter 4
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- [Encoder and octal-to-binary (8-to-3) encoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-to-binary-encoder) — Digital Logic, chapter 4, asked 2×
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