---
title: "Memory devices; PAL vs PLA"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:pal-vs-pla"
source: https://www.bctengineer.com/q/semester_3/digital_logic/pal-vs-pla
site: BCT Engineering
---

# Memory devices; PAL vs PLA

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2079 Bhadra, 2+4 marks
- Video: [Programmable Logic Devices - PROM, PLA, and PAL  by Dr. Alkesh Agrawal](https://www.youtube.com/watch?v=nemTyWV5lv8) — ETronicsLecturesbyDrAlkesh Agrawal
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/pal-vs-pla
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

What is a memory device? Distinguish between PAL and PLA memory devices.

## Short answer

PAL has a programmable AND array and a fixed OR array; PLA has both arrays programmable. PAL is faster and cheaper but less flexible, as product terms cannot be shared among outputs. PLA can share product terms, offering more flexibility for multi-output functions.

## Answer

A **memory device** is a device that stores binary information (bits) and lets it be read back, and in some types written. Each stored word is reached by an address. Examples: ROM, PROM, EPROM, RAM. Programmable logic devices such as PROM, PAL and PLA use the same array structure (an AND array that decodes the inputs and an OR array that holds the pattern), so they are studied with memories.

#### PAL vs PLA

**PLA (Programmable Logic Array):** both the AND array and the OR array are programmable.
**PAL (Programmable Array Logic):** the AND array is programmable but the OR array is **fixed** (each OR gate gets a fixed group of product terms).

| Point | PAL | PLA |
|---|---|---|
| AND array | Programmable | Programmable |
| OR array | Fixed | Programmable |
| Sharing of product terms | Not possible; each output has its own terms | Any product term can feed any output |
| Flexibility | Less | More |
| Speed | Faster (fewer programmable links in path) | Slower |
| Cost and complexity | Cheaper, simpler to make | Costlier, more complex |
| Terms per output | Limited to a fixed number | Limited only by total AND gates |
| Typical use | Simple glue logic, widely used (e.g. PAL16L8) | Multi-output functions with common terms |

```text
 PAL:  inputs -> [programmable AND] -> [fixed OR] -> out
 PLA:  inputs -> [programmable AND] -> [prog. OR] -> out
```

Example: if $F_1 = AB + C$ and $F_2 = AB + D$, a PLA generates $AB$ once and feeds it to both outputs; a PAL must generate $AB$ twice, once in each OR group.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is a memory device?
   A. A device that only computes arithmetic
   B. A device that only transmits data
   C. A device with no addressing
   D. A device that stores binary information and lets it be read back
   Answer: D. Words are reached by address. (Key point: Memory device)

2. Which statement is correct?
   A. PAL has programmable AND and fixed OR; PLA has both programmable
   B. PAL has fixed AND and programmable OR
   C. PLA has fixed OR
   D. Both have fixed AND arrays
   Answer: A. That is the key difference. (Key point: PAL vs PLA arrays)

3. Which device can share a product term between outputs?
   A. PAL
   B. PLA
   C. Both equally
   D. Neither
   Answer: B. In a PAL each output has its own fixed OR group. (Key point: Product term sharing)

4. How does PAL compare with PLA?
   A. Slower and costlier
   B. Slower but more flexible
   C. Faster and cheaper but less flexible
   D. Same speed and cost
   Answer: C. Fewer programmable links in the path make PAL faster. (Key point: Speed and cost)

## Related in Digital Logic

- [PROM vs PLA; functions using PAL](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aprom-pla-pal-functions) — Digital Logic, chapter 4

## Related in other subjects

- [Full vs partial address decoding for memory](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Afull-vs-partial-decoding) — Instrumentation II, chapter 2
- [Arbitration and memory-mapped vs standard I/O](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aarbitration-memory-mapped-io) — Embedded System, chapter 5
- [Device controller vs kernel; DMA](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Adevice-controller-vs-kernel-dma) — Operating System, chapter 6
- [USB interface chips: device vs host](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-interface-chips) — Instrumentation II, chapter 3