---
title: "Two 4-bit parallel adder"
subject: "Digital Logic"
chapter: 5
key: "semester_3/digital_logic:parallel-adder-4bit"
source: https://www.bctengineer.com/q/semester_3/digital_logic/parallel-adder-4bit
site: BCT Engineering
---

# Two 4-bit parallel adder

Digital Logic · Chapter 5: Arithmetic Circuits

- Asked in: 2076 Asoj, 5 marks
- Video: [4 Bit Parallel Adder using Full Adders](https://www.youtube.com/watch?v=NO7Gt8IDSGA) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/parallel-adder-4bit
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5

## Question

Explain the operation of two 4-bit parallel adder with neat diagram.

## Short answer

Four full adders cascade: carry-out of each stage feeds carry-in of the next, adding two 4-bit numbers at once. Two such adders form an 8-bit adder by connecting the lower adder's carry-out to the upper adder's carry-in. Sum bits appear after the carry ripples through all stages.

## Answer

A **4-bit parallel adder** adds two 4-bit binary numbers $A = A_3A_2A_1A_0$ and $B = B_3B_2B_1B_0$ at the same time. It uses four full adders connected in cascade: the carry-out of each full adder is the carry-in of the next higher stage. It is also called a ripple-carry adder (IC 7483 / 74283).

#### Diagram

```text
  A3 B3      A2 B2      A1 B1      A0 B0
   | |        | |        | |        | |
 +-----+    +-----+    +-----+    +-----+
 | FA3 |<C3-| FA2 |<C2-| FA1 |<C1-| FA0 |<- C0
 +-----+    +-----+    +-----+    +-----+
  |   |        |          |          |
 C4   S3       S2         S1         S0
```

Each full adder gives
$$
S_i = A_i \oplus B_i \oplus C_i, \qquad C_{i+1} = A_iB_i + B_iC_i + A_iC_i
$$

#### Operation

1. All bits of A and B are applied to the full adders at the same time; $C_0$ is normally 0.
2. FA0 adds $A_0$, $B_0$, $C_0$ and gives $S_0$ and $C_1$.
3. $C_1$ goes to FA1, which then gives $S_1$ and $C_2$, and so on.
4. FA3 gives $S_3$ and the final carry $C_4$, which is the fifth bit of the sum.
5. The output $C_4S_3S_2S_1S_0$ is valid only after the carry has passed through all stages.

**Example:** $A = 0110\ (6)$, $B = 0111\ (7)$:

| Stage | $A_i$ | $B_i$ | $C_i$ | $S_i$ | $C_{i+1}$ |
|---|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 |
| 2 | 1 | 1 | 1 | 1 | 1 |
| 3 | 0 | 0 | 1 | 1 | 0 |

Result $C_4S_3S_2S_1S_0 = 01101 = 13$.

#### Cascading two 4-bit adders

Two such 4-bit adders give an 8-bit adder: $C_4$ of the lower adder (bits 0–3) is connected to $C_0$ of the upper adder (bits 4–7).

**Limitation:** carry propagation delay. In the worst case the carry passes through every stage, so delay $\approx n \times t_{carry}$. A carry look-ahead adder removes this.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How are the full adders connected in a 4-bit parallel adder?
   A. Carry-out of each stage goes to carry-in of the next higher stage
   B. All carries go to FA0
   C. Carry-out goes to the next stage's sum
   D. Each stage has a separate carry source
   Answer: A. This cascade creates the ripple-carry. (Key point: Carry connection)

2. What is the sum output of a stage?
   A. Si = Ai Bi
   B. Si = Ai xor Bi xor Ci
   C. Si = Ai + Bi
   D. Si = Ci
   Answer: B. Sum is the XOR of the two bits and the carry-in. (Key point: Sum and carry)

3. What limits the speed of this adder?
   A. Number of AND gates for partial products
   B. The sum XOR gate only
   C. Carry propagation through all stages
   D. The input bit width of C0
   Answer: C. Worst-case delay is about n x t_carry. (Key point: Delay)

4. How are two 4-bit adders combined into an 8-bit adder?
   A. C4 of the upper goes to C0 of the lower
   B. Sums are joined by OR
   C. The two C0 inputs are tied
   D. C4 of the lower adder goes to C0 of the upper adder
   Answer: D. The lower-nibble carry-out feeds the upper-nibble carry-in. (Key point: Cascading)

## Related in Digital Logic

- [4-bit multiplier with parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abinary-multiplier-4bit) — Digital Logic, chapter 5
- [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5
- [3-bit multiplier with binary parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abinary-multiplier-3bit) — Digital Logic, chapter 5
- [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5
- [2-bit fast adder and its advantage](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-2bit) — Digital Logic, chapter 5
- [4-bit ripple carry adder and its problems](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aripple-carry-adder-problems) — Digital Logic, chapter 5

## Related in other subjects

- [Reactance diagram: 100 MVA base, two parallel paths](https://www.bctengineer.com/question.md?key=semester_4%2Fpower_system_analysis_i%3Areactance-diagram-90mva-two-paths) — Power System Analysis I, chapter 3
- [Need for parallel operation and dark lamp method](https://www.bctengineer.com/question.md?key=semester_5%2Felectric_machines_ii%3Aparallel-operation-need-dark-lamp) — Electric Machines II, chapter 1
- [Conditions for parallel operation of transformers](https://www.bctengineer.com/question.md?key=semester_4%2Felectrical_machines_i%3Atransformer-parallel-conditions-reasons) — Electrical Machines I, chapter 2
- [Conditions for parallel operation of transformers](https://www.bctengineer.com/question.md?key=semester_4%2Felectrical_machines%3Aparallel-operation-conditions) — Electrical Machines, chapter 2