---
title: "Parity bits and 3-bit even parity generator"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:parity-even-generator-3bit"
source: https://www.bctengineer.com/q/semester_3/digital_logic/parity-even-generator-3bit
site: BCT Engineering
---

# Parity bits and 3-bit even parity generator

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2076 Chaitra, 2+4 marks
- Video: [Parity Generator and Parity Checker Explained](https://www.youtube.com/watch?v=c8qAti1zBVQ) — ALL ABOUT ELECTRONICS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/parity-even-generator-3bit
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Describe the importance of parity bits in communication system. Explain 3 bits even parity generator circuit clearly.

## Short answer

A parity bit detects single-bit errors by making the total number of 1s even. For a 3-bit input A,B,C, the even parity generator is P = A ⊕ B ⊕ C. Implement with two XOR gates; P is 1 when data has odd parity, ensuring even parity overall.

## Answer

#### Importance of parity bits

A **parity bit** is an extra bit added to a data word so that the total number of 1s is even (even parity) or odd (odd parity). Its importance in communication:

- **Error detection:** noise can flip a bit during transmission. The receiver recounts the 1s; a wrong parity shows that an error occurred.
- **Simple and cheap:** only one extra bit and a few XOR gates are needed at each end.
- **Detects all single-bit (odd-number) errors**, which are the most common in many links. (It cannot detect two-bit errors and cannot correct errors.)
- Used in serial links (UART), memory (parity RAM) and as the base of Hamming codes.

#### 3-bit even parity generator

Inputs: data bits $A, B, C$. Output: parity bit $P$ chosen so that $A, B, C, P$ together have an **even** number of 1s.

| A | B | C | P |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |

$$
P = \Sigma m(1,2,4,7)
$$

The K-map is a checkerboard (no adjacent 1s), so it is simplified with XOR:

$$
\begin{aligned} P &= A'B'C + A'BC' + AB'C' + ABC \\ &= A'(B \oplus C) + A(B \odot C) \\ &= A \oplus B \oplus C \end{aligned}
$$

```text
 A --+
     +--[XOR]--+
 B --+         +--[XOR]--- P
 C ------------+
```

**Working:** $P$ is 1 when the data has an odd number of 1s, which makes the total even. Example: data $101$ has two 1s, so $P = 1 \oplus 0 \oplus 1 = 0$, and the transmitted word $1010$ has two 1s (even). At the receiver, a 4-bit checker $PEC = A \oplus B \oplus C \oplus P$ gives 0 for no error and 1 if a single bit has flipped.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the main purpose of a parity bit?
   A. Error correction
   B. Error detection
   C. Data compression
   D. Encryption
   Answer: B. A parity bit lets the receiver detect that a bit has flipped; it cannot locate or correct it. (Key point: Purpose of parity)

2. Which errors does a single parity bit fail to detect?
   A. A single-bit error
   B. Any odd number of bit errors
   C. Two-bit errors (an even number of errors)
   D. An error in the parity bit
   Answer: C. Two flips keep the parity unchanged, so even-count errors go unnoticed. (Key point: Limits of parity)

3. What is the output of the 3-bit even parity generator?
   A. P = A XNOR B XNOR C
   B. P = A AND B AND C
   C. P = A OR B OR C
   D. P = A XOR B XOR C
   Answer: D. P = A ⊕ B ⊕ C is 1 when the data has an odd number of 1s, making the total even. (Key point: Generator expression)

4. For data 101, what is the even parity bit P?
   A. 1
   B. 0
   C. Cannot be determined
   D. Equal to the middle bit
   Answer: B. 101 already has two 1s (even), so P = 1 ⊕ 0 ⊕ 1 = 0. (Key point: Worked example)

## Close variants set in other exams

- [Parity bits and 3-bit odd parity generator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparity-odd-generator-3bit) — Digital Logic, chapter 4, asked 2×

## Related in Digital Logic

- [3-bit even parity generator and 4-bit checker](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparity-generator-checker) — Digital Logic, chapter 4

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- [8085 ALP: odd parity transfer with bit change](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-odd-parity-transfer) — Microprocessor, chapter 2
- [Per unit circuit of three-generator system, 30 MVA base](https://www.bctengineer.com/question.md?key=semester_4%2Fpower_system_analysis_i%3Apu-circuit-30mva-g1-g2-g3) — Power System Analysis I, chapter 3