---
title: "3-bit even parity generator and 4-bit checker"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:parity-generator-checker"
source: https://www.bctengineer.com/q/semester_3/digital_logic/parity-generator-checker
site: BCT Engineering
---

# 3-bit even parity generator and 4-bit checker

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2068 Chaitra, 5 marks
- Video: [Q. 3.28: Derive the circuits for a three-bit parity generator and four-bit parity checker using an](https://www.youtube.com/watch?v=xG0A4Rp4usI) — Dr. Dhiman (Learn the art of problem solving) 
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/parity-generator-checker
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Design a 3-bit even parity generator and 4-bit even parity checker circuit.

## Short answer

A 3-bit even parity generator computes P = A ⊕ B ⊕ C using two XOR gates. A 4-bit even parity checker produces PEC = A ⊕ B ⊕ C ⊕ P with three XOR gates; PEC=0 indicates no error.

## Answer

Parity is used to detect single-bit errors. With **even parity**, the transmitted word (data + parity bit) always has an even number of 1s.

#### 3-bit even parity generator

Inputs $A, B, C$; output $P$ makes the total number of 1s even.

| A | B | C | P |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |

$$
\begin{aligned} P &= \Sigma m(1,2,4,7) = A'B'C + A'BC' + AB'C' + ABC \\ &= A'(B \oplus C) + A(B \odot C) = A \oplus B \oplus C \end{aligned}
$$

```text
 A --+
     +--[XOR]--+
 B --+         +--[XOR]--- P
 C ------------+
```

#### 4-bit even parity checker

The receiver gets $A, B, C, P$ and produces the parity error check $PEC$: 0 if the count of 1s is even (no error), 1 if odd (error).

| A B C P | No. of 1s | PEC |
|---|---|---|
| 0000 | 0 | 0 |
| 0001 | 1 | 1 |
| 0011 | 2 | 0 |
| 0111 | 3 | 1 |
| 1111 | 4 | 0 |
| (other rows follow the same rule) | | |

$PEC = 1$ for minterms 1, 2, 4, 7, 8, 11, 13, 14 (odd number of 1s). The K-map is a checkerboard, so

$$
PEC = A \oplus B \oplus C \oplus P = (A \oplus B) \oplus (C \oplus P)
$$

```text
 A --+
     +--[XOR]--+
 B --+         |
               +--[XOR]--- PEC
 C --+         |
     +--[XOR]--+
 P --+
```

#### Example

Data $110$: generator gives $P = 1 \oplus 1 \oplus 0 = 0$; sent word $1100$. If received correctly, $PEC = 1 \oplus 1 \oplus 0 \oplus 0 = 0$ (no error). If bit C flips (received $1110$), $PEC = 1$, so an error is flagged.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does a 3-bit even parity generator guarantee?
   A. Data plus parity bit contain an odd number of 1s
   B. The parity bit is always 0
   C. Data plus parity bit contain an even number of 1s
   D. Every data bit is copied twice
   Answer: C. Even parity chooses P so that the total count of 1s in the transmitted word is even. (Key point: Even parity rule)

2. What is the output equation of the 3-bit even parity generator?
   A. P = A.B.C
   B. P = A + B + C
   C. P = (A xor B) . C
   D. P = A xor B xor C
   Answer: D. P is 1 for minterms 1,2,4,7 (odd number of 1s in ABC), which is the three-input XOR. (Key point: Generator expression)

3. In the 4-bit checker PEC = A xor B xor C xor P, what does PEC = 1 mean?
   A. An odd number of 1s was received, so an error is flagged
   B. An even number of 1s, so no error
   C. The parity bit is 1
   D. The data is all 1s
   Answer: A. PEC is 0 for an even count of 1s (no error) and 1 for an odd count (error). (Key point: Checker output)

4. Data 110 is sent with even parity, and bit C flips so 1110 is received. What happens?
   A. P was 1 and PEC = 0
   B. P was 0 and the checker gives PEC = 1, flagging an error
   C. P was 0 and PEC = 0
   D. P was 1 and PEC = 1
   Answer: B. 1 xor 1 xor 0 = 0 gives P = 0. Received 1110 has three 1s, so PEC = 1. (Key point: Worked example)

## Related in Digital Logic

- [Parity bits and 3-bit even parity generator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparity-even-generator-3bit) — Digital Logic, chapter 4, asked 2×
- [Parity bits and 3-bit odd parity generator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparity-odd-generator-3bit) — Digital Logic, chapter 4, asked 2×
- [Circuit giving 2's complement of a 4-bit number](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Atwos-complement-generator) — Digital Logic, chapter 5

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- [8085 ALP: odd parity transfer with bit change](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-odd-parity-transfer) — Microprocessor, chapter 2
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