---
title: "Parity bits and 3-bit odd parity generator"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:parity-odd-generator-3bit"
source: https://www.bctengineer.com/q/semester_3/digital_logic/parity-odd-generator-3bit
site: BCT Engineering
---

# Parity bits and 3-bit odd parity generator

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2075 Asoj, 3+3 marks
- Video: [Parity Generator and Parity Checker Explained](https://www.youtube.com/watch?v=c8qAti1zBVQ) — ALL ABOUT ELECTRONICS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/parity-odd-generator-3bit
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Describe the importance of parity bits in communication system. Explain 3 bits odd parity generator circuit clearly.

## Short answer

Parity bits enable single-bit error detection. A 3-bit odd parity generator outputs P = (A⊕B⊕C)' to make total number of 1s odd. For even number of 1s in ABC, P=1; for odd, P=0.

## Answer

#### Importance of parity bits

A **parity bit** is one extra bit attached to a data word so that the total count of 1s is either even (even parity) or odd (odd parity). In communication systems it matters because:

- **Error detection:** noise or interference may flip a bit. The receiver checks the parity; a mismatch shows an error, and the data can be re-requested.
- **Low cost:** only one extra bit per word and a few XOR gates.
- **Single-bit errors are always detected** (in fact any odd number of errors).
- **Limits:** an even number of bit errors goes unnoticed, and the faulty bit cannot be located or corrected. Codes like Hamming code extend the parity idea to correct errors.
- Odd parity is often preferred because an all-zero word (e.g. a dead line) still carries a 1, so a stuck-at-0 line is detected.

#### 3-bit odd parity generator

Inputs $A, B, C$; output $P$ is chosen so that $A, B, C, P$ together contain an **odd** number of 1s.

| A | B | C | P |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |

$$
P = \Sigma m(0,3,5,6) = A'B'C' + A'BC + AB'C + ABC'
$$

The K-map has no adjacent 1s, so it is simplified with XOR/XNOR:

$$
\begin{aligned} P &= A'(B \odot C) + A(B \oplus C) \\ &= \overline{A \oplus B \oplus C} \end{aligned}
$$

```text
 A --+
     +--[XOR]--+
 B --+         +--[XNOR]--- P
 C ------------+
```

**Working:** if the data already has an odd number of 1s, $P = 0$; if even, $P = 1$. Example: data $110$ (two 1s) gives $P = \overline{1 \oplus 1 \oplus 0} = 1$, so the word $1101$ has three 1s (odd). The receiver's odd parity checker computes $\overline{A \oplus B \oplus C \oplus P}$, which is 0 when no error is present.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In odd parity, the parity bit is chosen so that the total number of 1s (data plus parity) is what?
   A. Even
   B. Odd
   C. Zero
   D. Always three
   Answer: B. Odd parity makes the whole word contain an odd number of 1s. (Key point: Odd parity definition)

2. What is the 3-bit odd parity generator output?
   A. P = A XOR B XOR C
   B. P = complement of (A XOR B XOR C)
   C. P = ABC
   D. P = A + B + C
   Answer: B. P = (A ⊕ B ⊕ C)', the XNOR of the three bits, so P = 1 when the data has an even number of 1s. (Key point: Generator expression)

3. For data 110, what is the odd parity bit and the transmitted word?
   A. P = 0, word 1100
   B. P = 1, word 1101
   C. P = 1, word 1100
   D. P = 0, word 1101
   Answer: B. 110 has two 1s (even), so P = 1 and 1101 has three 1s (odd). (Key point: Worked example)

4. Why is odd parity often preferred?
   A. It corrects errors
   B. An all-zero word (dead line) still carries a 1, so stuck-at-0 faults are detected
   C. It needs fewer gates than even parity
   D. It detects two-bit errors
   Answer: B. With odd parity an all-zero data word gets P = 1, so a dead line gives a detectable wrong word. (Key point: Why odd parity)

## Close variants set in other exams

- [Parity bits and 3-bit even parity generator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparity-even-generator-3bit) — Digital Logic, chapter 4, asked 2×

## Related in Digital Logic

- [3-bit even parity generator and 4-bit checker](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparity-generator-checker) — Digital Logic, chapter 4

## Related in other subjects

- [8085 ALP: odd parity transfer with bit change](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-odd-parity-transfer) — Microprocessor, chapter 2
- [(4,3) even parity code is linear, odd parity is not](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Aeven-odd-parity-linear-block) — Communication Systems, chapter 8
- [Per unit circuit of three-generator system, 30 MVA base](https://www.bctengineer.com/question.md?key=semester_4%2Fpower_system_analysis_i%3Apu-circuit-30mva-g1-g2-g3) — Power System Analysis I, chapter 3