--- title: "PISO register with 1001 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:piso-1001-data" source: https://www.bctengineer.com/q/semester_3/digital_logic/piso-1001-data site: BCT Engineering --- # PISO register with 1001 data Digital Logic · Chapter 7: Registers - Asked in: 2076 Asoj, 7 marks - Video: [Lec - 48: Shift Registers | SISO, SIPO, PISO, PIPO](https://www.youtube.com/watch?v=NjMX4hohyRI) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/piso-1001-data - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Explain how 1001 data can be stored and retrieved in PISO shift register with neat diagram and truth table. ## Short answer With SH/LD' low, the 4-bit PISO register loads 1001 in one clock (QA..QD = 1001). Setting SH/LD' high shifts bits right; the serial output QD yields 1, then 0, 0, 1 over the next three clocks, thus retrieving 1001 LSB first. ## Answer A **parallel-in serial-out (PISO) shift register** stores a word applied to its parallel inputs in one clock and then shifts it out one bit per clock. A 4-bit PISO register uses four D flip-flops; a SHIFT/LOAD' line selects (through AND-OR gates) either the parallel input or the previous stage's output for each flip-flop. #### Circuit ```text PA PB PC PD | | | | +-----+ +-----+ +-----+ +-----+ 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX | +-----+ | +-----+ | +-----+ | +-----+ | | | | | | | +-----+ | +-----+ | +-----+ | +-----+ |D QA|-+ |D QB|-+ |D QC|-+ |D QD|--> |> | |> | |> | |> | Serial +-----+ +-----+ +-----+ +-----+ out MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P SH/LD' and CLK are common to all stages. ``` ```text One stage (e.g. stage B): QA ---------->+-----+ SH/LD' --+--->| AND |--+ | +-----+ | +----+ | +->| OR |--> DB | +-----+ +->| | +NOT>| AND |--+ +----+ PB ---------->+-----+ DB = SH.QA + SH'.PB ``` - **SH/LD' = 0 (load):** the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time. - **SH/LD' = 1 (shift):** the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD. #### Storing and retrieving 1001 Parallel inputs: PA PB PC PD = 1 0 0 1 (PA = MSB, PD = LSB). 1. **Store (clock 1, SH/LD' = 0):** all bits load together: QA QB QC QD = 1001. The LSB (1) is already at the output QD. 2. **Retrieve (clocks 2, 3, 4, SH/LD' = 1):** each clock shifts right and a 0 enters QA. QD shows 0, 0, 1 in turn. 3. Serial output after clocks 1 to 4: **1, 0, 0, 1**, i.e. 1001 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits. | CLK | SH/LD' | QA | QB | QC | QD | Serial out | |---|---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | - | | 1 | Load | 1 | 0 | 0 | 1 | 1 | | 2 | Shift | 0 | 1 | 0 | 0 | 0 | | 3 | Shift | 0 | 0 | 1 | 0 | 0 | | 4 | Shift | 0 | 0 | 0 | 1 | 1 | | 5 | Shift | 0 | 0 | 0 | 0 | 0 | #### Timing diagram ```text 1 2 3 4 5 CLK _|‾|_|‾|_|‾|_|‾|_|‾| SH/LD' ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾| QA _|‾‾‾|______________ QB _____|‾‾‾|__________ QC _________|‾‾‾|______ QD _|‾‾‾|_______|‾‾‾|__ ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What enters QA while shifting? A. 0 B. 1 C. The previous QD D. The parallel bit PA Answer: A. In shift mode DA = 0 so zeros fill from the left. (Key point: Shift fill) 2. What is the serial output for clocks 1 to 4? A. 0, 1, 1, 0 B. 1, 0, 0, 1 C. 1, 1, 0, 0 D. 0, 0, 1, 1 Answer: B. LSB first, 1001 gives 1, 0, 0, 1. (Key point: Serial output) 3. After clock 3, what are QA QB QC QD? A. 0100 B. 1001 C. 0010 D. 0001 Answer: C. Load gives 1001, clock 2 gives 0100, clock 3 gives 0010. (Key point: Register state) ## Related in Digital Logic - [PISO shift register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1011-store-retrieve) — Digital Logic, chapter 7, asked 4× - [4-bit PISO shift register working](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-generic-circuit) — Digital Logic, chapter 7, asked 2× - [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7 - [SIPO register with 1001 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1001-store-retrieve) — Digital Logic, chapter 7 - [PISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1101-data) — Digital Logic, chapter 7, asked 2× - [PISO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1010-data) — Digital Logic, chapter 7 ## Related in other subjects - [Short note: Shift register and counter](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ashort-note-shift-register-counter) — Basic Electronics Engineering, chapter 6