--- title: "PISO register with 1010 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:piso-1010-data" source: https://www.bctengineer.com/q/semester_3/digital_logic/piso-1010-data site: BCT Engineering --- # PISO register with 1010 data Digital Logic · Chapter 7: Registers - Asked in: 2079 Bhadra, 6 marks - Video: [Shift Register (PISO Mode)](https://www.youtube.com/watch?v=7LmBcGiiYwk) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/piso-1010-data - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Explain the working function of PISO register with timing diagram of 1010 data input. ## Short answer A 4-bit PISO register loads parallel data 1010 with SH/LD'=0, then shifts bits out LSB first with SH/LD'=1. The serial output sequence is 0,1,0,1 over four clocks. The timing diagram shows the load control and the resulting QD waveform. ## Answer A **PISO register** takes a word in parallel (all bits together) and gives it out serially (one bit per clock). The 4-bit version uses four D flip-flops with a SHIFT/LOAD' control and an AND-OR selector at each D input. #### Circuit ```text PA PB PC PD | | | | +-----+ +-----+ +-----+ +-----+ 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX | +-----+ | +-----+ | +-----+ | +-----+ | | | | | | | +-----+ | +-----+ | +-----+ | +-----+ |D QA|-+ |D QB|-+ |D QC|-+ |D QD|--> |> | |> | |> | |> | Serial +-----+ +-----+ +-----+ +-----+ out MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P SH/LD' and CLK are common to all stages. ``` ```text One stage (e.g. stage B): QA ---------->+-----+ SH/LD' --+--->| AND |--+ | +-----+ | +----+ | +->| OR |--> DB | +-----+ +->| | +NOT>| AND |--+ +----+ PB ---------->+-----+ DB = SH.QA + SH'.PB ``` - **SH/LD' = 0 (load):** the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time. - **SH/LD' = 1 (shift):** the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD. #### Storing and retrieving 1010 Parallel inputs: PA PB PC PD = 1 0 1 0 (PA = MSB, PD = LSB). 1. **Store (clock 1, SH/LD' = 0):** all bits load together: QA QB QC QD = 1010. The LSB (0) is already at the output QD. 2. **Retrieve (clocks 2, 3, 4, SH/LD' = 1):** each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn. 3. Serial output after clocks 1 to 4: **0, 1, 0, 1**, i.e. 1010 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits. | CLK | SH/LD' | QA | QB | QC | QD | Serial out | |---|---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | - | | 1 | Load | 1 | 0 | 1 | 0 | 0 | | 2 | Shift | 0 | 1 | 0 | 1 | 1 | | 3 | Shift | 0 | 0 | 1 | 0 | 0 | | 4 | Shift | 0 | 0 | 0 | 1 | 1 | | 5 | Shift | 0 | 0 | 0 | 0 | 0 | #### Timing diagram ```text 1 2 3 4 5 CLK _|‾|_|‾|_|‾|_|‾|_|‾| SH/LD' ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾| QA _|‾‾‾|______________ QB _____|‾‾‾|__________ QC _|‾‾‾|___|‾‾‾|______ QD _____|‾‾‾|___|‾‾‾|__ ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does the AND-OR selector at each D input implement? A. D = P only B. D = SH.(Q of left FF) + SH'.P C. D = SH.P + SH'.Q of left FF D. D = Q of left FF.P Answer: B. SH selects shift from the left neighbour; SH' selects the parallel bit. (Key point: Selector logic) 2. For 1010, what is the first serial output after the load clock? A. 1, the MSB B. 1, the LSB C. 0, the LSB D. Nothing yet Answer: C. The LSB sits in QD after load, and here it is 0. (Key point: First output bit) 3. What is the complete serial output for clocks 1 to 4? A. 1, 0, 1, 0 B. 0, 0, 1, 1 C. 1, 1, 0, 0 D. 0, 1, 0, 1 Answer: D. 1010 is sent LSB first as 0, 1, 0, 1. (Key point: Output sequence) ## Related in Digital Logic - [PISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1101-data) — Digital Logic, chapter 7, asked 2× - [PISO shift register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1011-store-retrieve) — Digital Logic, chapter 7, asked 4× - [4-bit PISO shift register working](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-generic-circuit) — Digital Logic, chapter 7, asked 2× - [4-bit SIPO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1010-serial-in-serial-out) — Digital Logic, chapter 7, asked 2× - [PISO register with 1001 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1001-data) — Digital Logic, chapter 7 - [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9× ## Related in other subjects - [Timing diagram of LDA 2080H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-lda-2080h) — Microprocessor, chapter 2, asked 2× - [Timing diagram of LXI D, 2465H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-lxi-d-2465h) — Microprocessor, chapter 2, asked 2× - [Timing diagram of STA 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-sta-8050h) — Microprocessor, chapter 2 - [Timing diagram of STA, program time](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-sta-program-time) — Microprocessor, chapter 2