--- title: "PISO shift register with 1011 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:piso-1011-store-retrieve" source: https://www.bctengineer.com/q/semester_3/digital_logic/piso-1011-store-retrieve site: BCT Engineering --- # PISO shift register with 1011 data Digital Logic · Chapter 7: Registers - Asked in: 2081 Bhadra, 3+4 marks; 2081 Baisakh, 3+3 marks; 2080 Baisakh, 6 marks; 2070 Chaitra, 8 marks (asked 4 times) - Video: [Shift Register (PISO Mode)](https://www.youtube.com/watch?v=7LmBcGiiYwk) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/piso-1011-store-retrieve - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Explain briefly how 1011 data can be stored and retrieved in a 4-bit PISO shift register with its circuit and showing timing diagrams clearly. ## Short answer A 4-bit PISO register loads parallel data when SH/LD'=0 and shifts serially when SH/LD'=1. With inputs PA–PD = 1011, a load pulse sets QA–QD = 1011. Shifting then outputs LSB first at QD: 1,1,0,1 over three additional clocks. ## Answer A **parallel-in serial-out (PISO) shift register** loads all bits of a word at the same time (parallel) and then sends them out one bit per clock on a single line (serial). A 4-bit PISO register uses four D flip-flops, a SHIFT/LOAD' control and a 2-to-1 selector (two AND gates and an OR gate) in front of each flip-flop. #### Circuit ```text PA PB PC PD | | | | +-----+ +-----+ +-----+ +-----+ 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX | +-----+ | +-----+ | +-----+ | +-----+ | | | | | | | +-----+ | +-----+ | +-----+ | +-----+ |D QA|-+ |D QB|-+ |D QC|-+ |D QD|--> |> | |> | |> | |> | Serial +-----+ +-----+ +-----+ +-----+ out MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P SH/LD' and CLK are common to all stages. ``` ```text One stage (e.g. stage B): QA ---------->+-----+ SH/LD' --+--->| AND |--+ | +-----+ | +----+ | +->| OR |--> DB | +-----+ +->| | +NOT>| AND |--+ +----+ PB ---------->+-----+ DB = SH.QA + SH'.PB ``` - **SH/LD' = 0 (load):** the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time. - **SH/LD' = 1 (shift):** the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD. #### Storing and retrieving 1011 Parallel inputs: PA PB PC PD = 1 0 1 1 (PA = MSB, PD = LSB). 1. **Store (clock 1, SH/LD' = 0):** all bits load together: QA QB QC QD = 1011. The LSB (1) is already at the output QD. 2. **Retrieve (clocks 2, 3, 4, SH/LD' = 1):** each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn. 3. Serial output after clocks 1 to 4: **1, 1, 0, 1**, i.e. 1011 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits. | CLK | SH/LD' | QA | QB | QC | QD | Serial out | |---|---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | - | | 1 | Load | 1 | 0 | 1 | 1 | 1 | | 2 | Shift | 0 | 1 | 0 | 1 | 1 | | 3 | Shift | 0 | 0 | 1 | 0 | 0 | | 4 | Shift | 0 | 0 | 0 | 1 | 1 | | 5 | Shift | 0 | 0 | 0 | 0 | 0 | #### Timing diagram ```text 1 2 3 4 5 CLK _|‾|_|‾|_|‾|_|‾|_|‾| SH/LD' ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾| QA _|‾‾‾|______________ QB _____|‾‾‾|__________ QC _|‾‾‾|___|‾‾‾|______ QD _|‾‾‾‾‾‾‾|___|‾‾‾|__ ``` The whole 4-bit word is stored in one clock and retrieved in four clock periods; PISO registers are used for parallel-to-serial conversion, e.g. in serial communication (UART transmitter). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does SH/LD' = 0 do in the PISO register? A. Shifts the data right B. Selects the parallel inputs so all bits load at one clock C. Clears the register D. Disables the clock Answer: B. With SH/LD' = 0 the lower AND gates are enabled so D = P for each stage. (Key point: Mode control) 2. What is the input logic of one stage, such as stage B? A. DB = SH.QA + SH'.PB B. DB = SH.PB + SH'.QA C. DB = QA xor PB D. DB = SH + PB Answer: A. Shift selects the previous stage's Q; load selects the parallel input. (Key point: Mux per stage) 3. For 1011 loaded in parallel, what is the serial output order after clocks 1 to 4? A. 1, 0, 1, 1 B. 1, 1, 0, 1 (LSB first) C. 1, 1, 1, 0 D. 0, 1, 1, 0 Answer: B. The LSB (1) is at QD after loading, then shifts bring 1, 0, 1. (Key point: Serial output order) 4. How many clocks are needed to load and retrieve a 4-bit word until the last bit is out? A. 1 load clock plus 3 shift clocks B. 8 clocks C. 1 clock D. 4 load clocks Answer: A. One clock loads (and shows the first bit); n-1 = 3 more clocks deliver the rest. (Key point: Clocks needed) ## Related in Digital Logic - [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7 - [4-bit PISO shift register working](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-generic-circuit) — Digital Logic, chapter 7, asked 2× - [PISO register with 1001 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1001-data) — Digital Logic, chapter 7 - [PISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1101-data) — Digital Logic, chapter 7, asked 2× - [SISO register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1011-data) — Digital Logic, chapter 7, asked 9× - [PISO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1010-data) — Digital Logic, chapter 7 ## Related in other subjects - [4-bit R-2R ladder bit voltages and 1011 output](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Ar2r-4bit-12v-1011) — Advanced Electronics, chapter 3 - [Short note: Shift register and counter](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ashort-note-shift-register-counter) — Basic Electronics Engineering, chapter 6