--- title: "PISO register with 1101 data" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:piso-1101-data" source: https://www.bctengineer.com/q/semester_3/digital_logic/piso-1101-data site: BCT Engineering --- # PISO register with 1101 data Digital Logic · Chapter 7: Registers - Asked in: 2078 Bhadra, 6 marks; 2075 Chaitra, 6 marks (asked 2 times) - Video: [Shift Register (PISO Mode)](https://www.youtube.com/watch?v=7LmBcGiiYwk) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/piso-1101-data - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Draw a 4 bit PISO shift register and explain its operation along with timing waveform with 1101 data load in input. ## Short answer A 4-bit PISO register loads four bits in parallel when SH/LD' is low, then shifts them out serially LSB first when SH/LD' is high. For data 1101 loaded on clock 1, serial output on clocks 1–4 is 1,0,1,1. The timing diagram illustrates the load and shift waveforms. ## Answer A **PISO (parallel-in serial-out) shift register** accepts all bits of a word at once and shifts them out one bit per clock. It is built from four D flip-flops; a control line SHIFT/LOAD' selects, through AND-OR gates, whether each flip-flop takes its parallel input bit (load) or the output of the flip-flop on its left (shift). #### Circuit ```text PA PB PC PD | | | | +-----+ +-----+ +-----+ +-----+ 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX | +-----+ | +-----+ | +-----+ | +-----+ | | | | | | | +-----+ | +-----+ | +-----+ | +-----+ |D QA|-+ |D QB|-+ |D QC|-+ |D QD|--> |> | |> | |> | |> | Serial +-----+ +-----+ +-----+ +-----+ out MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P SH/LD' and CLK are common to all stages. ``` ```text One stage (e.g. stage B): QA ---------->+-----+ SH/LD' --+--->| AND |--+ | +-----+ | +----+ | +->| OR |--> DB | +-----+ +->| | +NOT>| AND |--+ +----+ PB ---------->+-----+ DB = SH.QA + SH'.PB ``` - **SH/LD' = 0 (load):** the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time. - **SH/LD' = 1 (shift):** the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD. #### Storing and retrieving 1101 Parallel inputs: PA PB PC PD = 1 1 0 1 (PA = MSB, PD = LSB). 1. **Store (clock 1, SH/LD' = 0):** all bits load together: QA QB QC QD = 1101. The LSB (1) is already at the output QD. 2. **Retrieve (clocks 2, 3, 4, SH/LD' = 1):** each clock shifts right and a 0 enters QA. QD shows 0, 1, 1 in turn. 3. Serial output after clocks 1 to 4: **1, 0, 1, 1**, i.e. 1101 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits. | CLK | SH/LD' | QA | QB | QC | QD | Serial out | |---|---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | - | | 1 | Load | 1 | 1 | 0 | 1 | 1 | | 2 | Shift | 0 | 1 | 1 | 0 | 0 | | 3 | Shift | 0 | 0 | 1 | 1 | 1 | | 4 | Shift | 0 | 0 | 0 | 1 | 1 | | 5 | Shift | 0 | 0 | 0 | 0 | 0 | #### Timing diagram ```text 1 2 3 4 5 CLK _|‾|_|‾|_|‾|_|‾|_|‾| SH/LD' ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾| QA _|‾‾‾|______________ QB _|‾‾‾‾‾‾‾|__________ QC _____|‾‾‾‾‾‾‾|______ QD _|‾‾‾|___|‾‾‾‾‾‾‾|__ ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In the PISO register, what does SH/LD' = 0 do? A. Shifts the data one place right B. Clears all flip-flops C. Loads the parallel inputs into all flip-flops at one clock edge D. Holds the data Answer: C. SH/LD' = 0 enables the lower AND gates so each D takes its parallel input. (Key point: Mode control) 2. After the load clock for 1101, what is already at the serial output QD? A. The MSB, 1 which is PA, with QD = 0 B. Nothing, until the 4th clock C. 0, because QD is cleared D. The LSB, 1 Answer: D. Loading puts PD (the LSB) straight into QD, so it is the first output bit. (Key point: Load operation) 3. What is the serial output over clocks 1 to 4 for 1101? A. 1, 0, 1, 1 B. 1, 1, 0, 1 C. 0, 1, 1, 0 D. 1, 0, 0, 1 Answer: A. 1101 is sent LSB first as 1, 0, 1, 1. (Key point: Serial output) 4. After clock 2 (first shift), what are QA QB QC QD? A. 1101 B. 0110 C. 0011 D. 1011 Answer: B. Loaded 1101 shifts right with a 0 entering QA, giving 0110. (Key point: Shift behaviour) ## Related in Digital Logic - [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7 - [PISO shift register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1011-store-retrieve) — Digital Logic, chapter 7, asked 4× - [4-bit PISO shift register working](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-generic-circuit) — Digital Logic, chapter 7, asked 2× - [SIPO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-1101-data) — Digital Logic, chapter 7, asked 2× - [SISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-1101-data) — Digital Logic, chapter 7, asked 10× - [PISO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1010-data) — Digital Logic, chapter 7