--- title: "4-bit PISO shift register working" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:piso-generic-circuit" source: https://www.bctengineer.com/q/semester_3/digital_logic/piso-generic-circuit site: BCT Engineering --- # 4-bit PISO shift register working Digital Logic · Chapter 7: Registers - Asked in: 2075 Chaitra, 6 marks; 2073 Shrawan, 7 marks (asked 2 times) - Video: [Shift Register (PISO Mode)](https://www.youtube.com/watch?v=7LmBcGiiYwk) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/piso-generic-circuit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Draw the circuit diagram and explain the working principle of 4-bit parallel in serial out (PISO) shift register. ## Short answer The 4-bit PISO register contains D flip-flops with input selectors controlled by SH/LD'. Setting SH/LD'=0 loads parallel data in one clock; SH/LD'=1 enables right-shift, sending bits out serially at QD LSB first. For example, loading 1011 yields serial output 1,1,0,1 after four clocks. ## Answer A **4-bit parallel-in serial-out (PISO) shift register** stores a 4-bit word applied on four parallel lines in one clock and then shifts it out bit by bit on a single serial output. It uses four D flip-flops, a common clock and a SHIFT/LOAD' control that, through a 2-to-1 AND-OR selector at each D input, chooses between parallel data and the output of the previous stage. The working is illustrated with the word 1011. #### Circuit ```text PA PB PC PD | | | | +-----+ +-----+ +-----+ +-----+ 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX | +-----+ | +-----+ | +-----+ | +-----+ | | | | | | | +-----+ | +-----+ | +-----+ | +-----+ |D QA|-+ |D QB|-+ |D QC|-+ |D QD|--> |> | |> | |> | |> | Serial +-----+ +-----+ +-----+ +-----+ out MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P SH/LD' and CLK are common to all stages. ``` ```text One stage (e.g. stage B): QA ---------->+-----+ SH/LD' --+--->| AND |--+ | +-----+ | +----+ | +->| OR |--> DB | +-----+ +->| | +NOT>| AND |--+ +----+ PB ---------->+-----+ DB = SH.QA + SH'.PB ``` - **SH/LD' = 0 (load):** the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time. - **SH/LD' = 1 (shift):** the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD. #### Storing and retrieving 1011 Parallel inputs: PA PB PC PD = 1 0 1 1 (PA = MSB, PD = LSB). 1. **Store (clock 1, SH/LD' = 0):** all bits load together: QA QB QC QD = 1011. The LSB (1) is already at the output QD. 2. **Retrieve (clocks 2, 3, 4, SH/LD' = 1):** each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn. 3. Serial output after clocks 1 to 4: **1, 1, 0, 1**, i.e. 1011 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits. | CLK | SH/LD' | QA | QB | QC | QD | Serial out | |---|---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | - | | 1 | Load | 1 | 0 | 1 | 1 | 1 | | 2 | Shift | 0 | 1 | 0 | 1 | 1 | | 3 | Shift | 0 | 0 | 1 | 0 | 0 | | 4 | Shift | 0 | 0 | 0 | 1 | 1 | | 5 | Shift | 0 | 0 | 0 | 0 | 0 | #### Timing diagram ```text 1 2 3 4 5 CLK _|‾|_|‾|_|‾|_|‾|_|‾| SH/LD' ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾| QA _|‾‾‾|______________ QB _____|‾‾‾|__________ QC _|‾‾‾|___|‾‾‾|______ QD _|‾‾‾‾‾‾‾|___|‾‾‾|__ ``` Working principle in short: **load in parallel, then shift right**. A 4-bit word needs 1 load clock plus 3 shift clocks to transmit all bits. PISO registers are used for parallel-to-serial conversion in data transmission. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does the SHIFT/LOAD' line decide? A. Whether the clock is enabled B. Whether the output is inverted C. Whether each D input takes the parallel data or the previous stage output D. Which flip-flop is cleared Answer: C. Through the AND-OR selector, it picks parallel data (load) or the left neighbour's Q (shift). (Key point: Mode control) 2. Which expression gives the D input of stage B? A. DB = SH.PB + SH'.QA B. DB = QA.PB C. DB = SH + PB D. DB = SH.QA + SH'.PB Answer: D. With SH = 1 it takes QA (shift); with SH = 0 it takes PB (load). (Key point: Stage logic) 3. For the word 1011, what is the serial output for clocks 1 to 4? A. 1, 1, 0, 1 B. 1, 0, 1, 1 C. 1, 0, 1, 0 D. 0, 1, 1, 0 Answer: A. The LSB comes out first, so 1011 is sent as 1, 1, 0, 1. (Key point: Serial output) 4. How many clocks are needed to transmit all bits of a 4-bit word? A. 4 load clocks plus 4 shift clocks B. 1 load clock plus 3 shift clocks C. 1 load clock only D. 3 load clocks plus 1 shift clock Answer: B. One clock loads the word and n - 1 = 3 more clocks deliver the remaining bits. (Key point: Number of clocks) ## Related in Digital Logic - [Shift register and 4-bit PISO operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashift-register-piso) — Digital Logic, chapter 7 - [PISO shift register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1011-store-retrieve) — Digital Logic, chapter 7, asked 4× - [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9× - [Shift register uses; 4-bit ring counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aring-counter-4bit) — Digital Logic, chapter 7 - [4-bit bidirectional shift register](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abidirectional-shift-register) — Digital Logic, chapter 7 - [SISO and SIPO shift register circuits](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-sipo-circuit) — Digital Logic, chapter 7 ## Related in other subjects - [Working principle of dc generator with diagram](https://www.bctengineer.com/question.md?key=semester_4%2Felectrical_machines%3Adc-generator-principle-diagram) — Electrical Machines, chapter 3 - [Short note: Shift register and counter](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ashort-note-shift-register-counter) — Basic Electronics Engineering, chapter 6 - [Short note: serial and parallel interface](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aserial-parallel-interface) — Microprocessor, chapter 4 - [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3