---
title: "PLA and full subtractor using PLA"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:pla-full-subtractor"
source: https://www.bctengineer.com/q/semester_3/digital_logic/pla-full-subtractor
site: BCT Engineering
---

# PLA and full subtractor using PLA

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2078 Bhadra, 2+3 marks
- Video: [Full Subtractor Using PLA | Design  full subtractor using PLA | PLA as full subtractor](https://www.youtube.com/watch?v=U9wWiTC27sE) — Techno Tutorials ( e-Learning)
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/pla-full-subtractor
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Define PLA (Programmable Logic Array). Implement the full subtractor using PLA.

## Short answer

PLA (Programmable Logic Array) contains programmable AND and OR arrays. For a full subtractor, difference D = A⊕B⊕Bin, borrow output Bo = A'Bin + A'B + BBin. Implement with 7 product terms in the AND array, then OR arrays sum appropriate terms.

## Answer

A **PLA (Programmable Logic Array)** is a programmable logic device with a **programmable AND array** followed by a **programmable OR array**. The AND array generates the needed product terms of the inputs and the OR array sums any of them for each output, so it can implement several SOP functions that share product terms.

#### Full subtractor using PLA

Inputs $A$ (minuend), $B$ (subtrahend), $B_{in}$ (borrow in). Outputs: difference $D$ and borrow out $B_o$.

| A | B | $B_{in}$ | D | $B_o$ |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 |

$$
D = \Sigma m(1,2,4,7) = A'B'B_{in} + A'BB_{in}' + AB'B_{in}' + ABB_{in}
$$
$$
B_o = \Sigma m(1,2,3,7) = A'B_{in} + A'B + BB_{in}
$$

$D$ (XOR) cannot be simplified, so 4 + 3 = **7 product terms** are needed.

**PLA programming table** (1 = true input, 0 = complemented, – = not used):

| Term | Product | A | B | $B_{in}$ | D | $B_o$ |
|---|---|---|---|---|---|---|
| 1 | $A'B'B_{in}$ | 0 | 0 | 1 | 1 | – |
| 2 | $A'BB_{in}'$ | 0 | 1 | 0 | 1 | – |
| 3 | $AB'B_{in}'$ | 1 | 0 | 0 | 1 | – |
| 4 | $ABB_{in}$ | 1 | 1 | 1 | 1 | – |
| 5 | $A'B_{in}$ | 0 | – | 1 | – | 1 |
| 6 | $A'B$ | 0 | 1 | – | – | 1 |
| 7 | $BB_{in}$ | – | 1 | 1 | – | 1 |

```text
A  B  Bin (true and complement lines)
|  |  |
[ AND array: P1 ... P7 ]   (programmed)
   |
[ OR array ]
   OR1 = P1+P2+P3+P4  ---> D
   OR2 = P5+P6+P7     ---> Bo
```

So a 3-input, 7-product-term, 2-output PLA implements the full subtractor.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What defines a PLA?
   A. Fixed AND array and programmable OR array
   B. Both the AND array and the OR array are programmable
   C. Programmable AND array and fixed OR array
   D. Both arrays are fixed
   Answer: B. A PLA has a programmable AND plane followed by a programmable OR plane. (Key point: PLA definition)

2. Which expression gives the full subtractor difference D?
   A. Σm(1,2,3,7)
   B. Σm(0,3,5,6)
   C. Σm(1,2,4,7), an XOR of A, B and Bin
   D. A'B + BBin
   Answer: C. D is 1 when an odd number of inputs are 1: minterms 1, 2, 4, 7. It is A xor B xor Bin. (Key point: Difference function)

3. Why does the PLA for the full subtractor need 7 product terms?
   A. D needs 4 minterm terms (XOR cannot be simplified) and Bo needs 3 simplified terms
   B. Each of the 8 minterms needs its own term
   C. D needs 3 terms and Bo needs 4
   D. Only 4 terms are needed since they are all shared
   Answer: A. 4 + 3 = 7: the XOR has no simplification, while Bo = A'Bin + A'B + BBin has 3 terms. (Key point: Product term count)

## Related in Digital Logic

- [Full subtractor using a 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-1to4-demux) — Digital Logic, chapter 4, asked 6×
- [Full subtractor using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-2x4-decoder) — Digital Logic, chapter 4, asked 4×
- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4
- [Full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-half-subtractors) — Digital Logic, chapter 5
- [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5
- [PLA for F1 = Σm(3,5,6,7), F2 = Σm(0,2,4,7)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apla-two-functions) — Digital Logic, chapter 4

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- [Linear queue using array](https://www.bctengineer.com/question.md?key=semester_4%2Fdata_structure_and_algorithm%3Alinear-queue-array-implementation) — Data Structure and Algorithm, chapter 2, asked 2×