--- title: "Positive edge JK flip-flop and its drawbacks" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:positive-edge-jk-drawbacks" source: https://www.bctengineer.com/q/semester_3/digital_logic/positive-edge-jk-drawbacks site: BCT Engineering --- # Positive edge JK flip-flop and its drawbacks Digital Logic · Chapter 6: Flip Flops - Asked in: 2069 Chaitra, 7+1 marks - Video: [Lec -32: Introduction to JK Flip Flop | JK flip flop full explanation | Digital Electronics](https://www.youtube.com/watch?v=qU7x1XLjhn4) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/positive-edge-jk-drawbacks - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Draw the circuit diagram and explain the operation of positive edge triggered JK flip-flop. What are the drawbacks of JK flip-flop? ## Short answer In a level-triggered JK flip-flop with J=K=1, the output toggles repeatedly while the clock is high (race-around condition). Edge-triggered designs eliminate this but rely on a narrow pulse hard to control and use more gates than a D flip-flop. ## Answer A **positive edge-triggered J-K flip-flop** samples J and K only at the rising (0 to 1) edge of the clock. It is built from a clocked J-K NAND circuit whose clock input is a narrow pulse produced by an edge detector. #### Circuit diagram **Edge detector (pulse-transition detector):** ```text CLK --+---------------->+-----+ | | AND |---> CLK* +--->[ NOT ]----->+-----+ (delay dt) CLK* = CLK . CLK'(delayed): a spike of width about dt at every rising edge of CLK ``` The NOT gate delays and inverts CLK. Just after CLK rises, the inverter output is still 1 for its propagation delay $\Delta t$, so the AND gate gives a narrow spike CLK*. After the rising edge, at the falling edge and at all other times, CLK* = 0. **J-K section (NAND gates):** ```text +------+ S* +------+ J -------| |----->| | CLK* ----| NAND | | NAND |-----> Q Q' ------| G1 | Q'->| G3 | +------+ +------+ +------+ R* +------+ K -------| |----->| | CLK* ----| NAND | | NAND |-----> Q' Q ------| G2 | Q-->| G4 | +------+ +------+ G3 and G4 are cross-coupled (NAND latch). Q' is fed back to G1, Q is fed back to G2. ``` ```text +---------+ J ---| J Q |--- Q CLK -|> | K ---| K Q' |--- Q' +---------+ '>' = edge triggered (a bubble 'o>' means negative edge triggered) ``` #### Operation G1 has inputs J, CLK*, Q'; G2 has inputs K, CLK*, Q. G3-G4 form an active-low S'-R' latch. 1. **No rising edge (CLK* = 0):** G1 = G2 = 1, latch holds: Q unchanged whatever J, K are. 2. **J = 0, K = 0:** G1 = G2 = 1 even at the edge: **no change**. 3. **J = 0, K = 1:** at the edge, G2 = (K·CLK*·Q)' = 0 if Q = 1, so the latch **resets** (Q = 0). If Q was 0 it stays 0. 4. **J = 1, K = 0:** at the edge, G1 = (J·CLK*·Q')' = 0 if Q = 0, so the latch **sets** (Q = 1). If Q was 1 it stays 1. 5. **J = 1, K = 1:** if Q = 0, G1 fires and sets; if Q = 1, G2 fires and resets. Output **toggles**. Since CLK* lasts less than the propagation delay of the latch, the new output arrives after CLK* is over, so only one toggle happens per edge. **Truth table** | CLK | J | K | Q+ | Action | |---|---|---|---|---| | no edge | x | x | Q | No change | | edge | 0 | 0 | Q | No change (hold) | | edge | 0 | 1 | 0 | Reset | | edge | 1 | 0 | 1 | Set | | edge | 1 | 1 | Q' | Toggle | $$ Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n $$ **Timing diagram** (Q initially 0, changes only at rising edges) ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| J ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾| K _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾| Q _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__ ``` #### Drawbacks of J-K flip-flop - In a **level-triggered** J-K flip-flop with J = K = 1, the output toggles many times while the clock is high (**race-around condition**); edge triggering or master-slave construction is needed to avoid it. - Edge triggering depends on a very narrow pulse whose width (gate delay) is hard to control; it needs two inputs and more gates than a D flip-flop, so it is not convenient for simple data storage. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is the CLK* pulse formed? A. CLK ANDed with J B. CLK divided by two C. CLK ORed with Q D. CLK ANDed with delayed inverted CLK, a spike of about the NOT gate delay Answer: D. A spike appears just after each rising edge. (Key point: Edge detector) 2. With J = 0, K = 1 at the edge and Q = 1, which gate acts? A. G2 gives 0 and resets Q to 0 B. G1 sets C. No gate D. Both set Answer: A. G2 has K, CLK*, Q all 1, so its output is 0, resetting the latch. (Key point: Reset) 3. Why is Q unchanged between rising edges whatever J and K are? A. J and K are grounded B. CLK* = 0 so G1 = G2 = 1 and the latch holds C. The latch is disabled forever D. Q is fixed Answer: B. With CLK* low, both NAND outputs are 1, which holds the latch. (Key point: Hold between edges) 4. Which are drawbacks of the JK flip-flop? A. It cannot toggle B. It has no invalid state but cannot store data C. Race-around in level-triggered form, a hard-to-control narrow pulse width, and more gates than D D. It needs a negative supply Answer: C. Level-triggered JK suffers race-around, and edge triggering relies on a narrow pulse and extra gates and inputs. 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