---
title: "Positive/negative logic; XNOR using NAND"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:positive-negative-logic-xnor-nand"
source: https://www.bctengineer.com/q/semester_3/digital_logic/positive-negative-logic-xnor-nand
site: BCT Engineering
---

# Positive/negative logic; XNOR using NAND

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2080 Bhadra, 2+4 marks
- Video: [Q. 2.26: Show that a positive logic NAND gate is a negative logic NOR gate and vice versa.](https://www.youtube.com/watch?v=zgSE2XH2b5Q) — Dr. Dhiman (Learn the art of problem solving) 
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/positive-negative-logic-xnor-nand
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

Define positive and negative logic. Realize X-NOR gate using NAND gates only.

## Short answer

Positive logic: HIGH=1, LOW=0; negative logic: HIGH=0, LOW=1. An XNOR gate is built with five NAND gates: four gates form XOR (G4 = A⊕B), and a fifth NAND with both inputs tied to G4 inverts it, yielding Y = ¬(A⊕B) = A⊙B.

## Answer

#### Positive and negative logic
- **Positive logic:** HIGH voltage = logic 1, LOW voltage = logic 0 (e.g. TTL: +5 V = 1, 0 V = 0).
- **Negative logic:** HIGH voltage = logic 0, LOW voltage = logic 1 (e.g. +5 V = 0, 0 V = 1).

The same physical gate performs a different logic function in the two systems, because changing the convention complements every input and output. Example: a gate whose output is HIGH only when both inputs are HIGH is an AND gate in positive logic but an OR gate in negative logic.

#### XNOR using NAND gates only
$Y = A \odot B = \overline{A \oplus B}$. First build XOR with 4 NAND gates, then invert it with a fifth NAND gate whose two inputs are tied together ($\overline{X \cdot X} = \bar X$). Minimum: **5 NAND gates**.

$$
\begin{aligned} G_1 &= \overline{AB} \\ G_2 &= \overline{A G_1} \\ G_3 &= \overline{B G_1} \\ G_4 &= \overline{G_2 G_3} = A \oplus B \\ Y &= \overline{G_4 \cdot G_4} = \overline{A \oplus B} = AB + \bar A \bar B \end{aligned}
$$

```text
 A --+-----------[NAND G2]--+
     |              |       |
     +--[NAND G1]---+       +--[NAND G4]--+--[NAND G5]-- Y
     |              |       |             +--|
 B --+-----------[NAND G3]--+       (inputs tied: NOT)
```

| A | B | $G_1$ | $G_2$ | $G_3$ | $G_4$ | Y |
|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 | 1 |

Y is 1 when both inputs are equal, which is XNOR.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Negative logic means?
   A. HIGH = 1
   B. Only 0 V
   C. HIGH = 0, LOW = 1
   D. No levels
   Answer: C. Reverse of positive. (Key point: Logic types)

2. A positive AND is what in negative logic?
   A. NAND
   B. AND
   C. OR
   D. NOR
   Answer: C. Complementing all bits dualises it. (Key point: Same gate)

3. Minimum NANDs for XNOR?
   A. 4
   B. 5
   C. 3
   D. 6
   Answer: B. 4 for XOR plus 1 inverter. (Key point: XNOR count)

4. How is the 5th NAND used?
   A. Inputs tied together to act as NOT
   B. Left floating
   C. As an AND
   D. Inputs tied to ground
   Answer: A. (X X)' = X'. (Key point: Inverter)

## Close variants set in other exams

- [Positive/negative logic; Ex-NOR using NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apositive-negative-logic-xnor-nor) — Digital Logic, chapter 2, asked 2×

## Related in Digital Logic

- [3-input XNOR using NOR gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xnor-nor) — Digital Logic, chapter 2
- [De Morgan; positive NAND equals negative NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-positive-nand-negative-nor) — Digital Logic, chapter 2
- [Universal gates; positive and negative logic](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Auniversal-gates-positive-logic) — Digital Logic, chapter 2
- [De Morgan's laws; XNOR using NOR gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xnor-nor) — Digital Logic, chapter 2
- [De Morgan; NOR gate from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-nor-from-nand) — Digital Logic, chapter 2
- [3-input XOR using NAND gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xor-nand) — Digital Logic, chapter 2, asked 2×

## Related in other subjects

- [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6
- [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6
- [CMOS NAND, NOR (and NOT) circuits](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acmos-nand-nor-circuits) — Embedded System, chapter 8, asked 2×