---
title: "4:2 priority encoder"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:priority-encoder-4to2"
source: https://www.bctengineer.com/q/semester_3/digital_logic/priority-encoder-4to2
site: BCT Engineering
---

# 4:2 priority encoder

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2079 Baisakh, 6 marks
- Video: [U2 L7.3 | | Priority Encoder | 4 to 2  Priority Encoder | Priority Encoder: Truth Table, K-Map](https://www.youtube.com/watch?v=PKvCCzxew2g) — Techno Tutorials ( e-Learning)
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/priority-encoder-4to2
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Design the logic circuit for 4:2 Priority Encoder.

## Short answer

4:2 priority encoder (D3 highest). X = D2 + D3, Y = D3 + D1·D2', Valid V = D0+D1+D2+D3. Circuit: OR gate for X, NOT and AND for Y's product term then OR with D3, and 4-input OR for V.

## Answer

A **4:2 priority encoder** has four inputs $D_0$–$D_3$ and gives the 2-bit code $XY$ of the highest-priority active input. Here $D_3$ has the highest priority and $D_0$ the lowest. A valid bit $V$ shows that at least one input is 1 (otherwise $XY$ is meaningless).

#### Truth table (X = don't care)

| $D_3$ | $D_2$ | $D_1$ | $D_0$ | X | Y | V |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | X | X | 0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | X | 0 | 1 | 1 |
| 0 | 1 | X | X | 1 | 0 | 1 |
| 1 | X | X | X | 1 | 1 | 1 |

#### K-maps (rows $D_3D_2$, columns $D_1D_0$)

For X:

| $D_3D_2$ \ $D_1D_0$ | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | X | 0 | 0 | 0 |
| 01 | 1 | 1 | 1 | 1 |
| 11 | 1 | 1 | 1 | 1 |
| 10 | 1 | 1 | 1 | 1 |

$$
X = D_2 + D_3
$$

For Y:

| $D_3D_2$ \ $D_1D_0$ | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | X | 0 | 1 | 1 |
| 01 | 0 | 0 | 0 | 0 |
| 11 | 1 | 1 | 1 | 1 |
| 10 | 1 | 1 | 1 | 1 |

$$
Y = D_3 + D_1 D_2'
$$

Valid output:

$$
V = D_0 + D_1 + D_2 + D_3
$$

#### Logic circuit

```text
 D3 ------+-----------------[OR]---- X
 D2 ---+--|-----------------^
       |  |
       +-[NOT]--+
 D1 ----------[AND]--+
                     +--[OR]------- Y
 D3 -----------------+

 D0,D1,D2,D3 -------[OR 4]--------- V
```

**Check:** $D_3D_2D_1D_0 = 0110$: $X = 1$, $Y = 0 + 1\cdot 0 = 0$, so output $10$ = input 2, the highest active one. $D_3 = 1$ gives $XY = 11$ whatever the others are. All cases were verified against the table.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In the 4:2 priority encoder, if D3 = 1 and D1 = 1 at the same time, what is the output XY?
   A. 01
   B. 10
   C. 11
   D. 00
   Answer: C. D3 has the highest priority, so XY = 11 whatever the other inputs are. (Key point: Priority rule)

2. Which expression gives output X?
   A. D2 + D3
   B. D1 + D0
   C. D3 D2
   D. D3 + D1
   Answer: A. X is 1 whenever the highest active input is 2 or 3, so X = D2 + D3. (Key point: Equation for X)

3. Why does Y = D3 + D1 D2' include D2' in the second term?
   A. D1 only counts when the higher input D2 is 0
   B. D2 must be 1 to encode input 1
   C. To make V equal to 1
   D. Because D0 is the highest priority
   Answer: A. If D2 were 1 the highest input would be 2 (code 10, Y = 0), so D1 sets Y only when D2 = 0. (Key point: Equation for Y)

4. What is the purpose of the valid bit V = D0 + D1 + D2 + D3?
   A. It gives the code of the lowest input
   B. It shows whether at least one input is active, so XY is meaningful
   C. It resolves two inputs being active
   D. It inverts the output code
   Answer: B. When all inputs are 0 the code XY is meaningless; V = 0 flags that situation. (Key point: Valid bit V)

## Related in Digital Logic

- [Priority encoder; 4-to-2 priority encoder logic](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-4to2-expressions) — Digital Logic, chapter 4
- [Octal priority encoder design](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-priority-encoder-design) — Digital Logic, chapter 4, asked 3×
- [Priority encoder; "e" and "f" segments](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-e-f-segments) — Digital Logic, chapter 4
- [Priority encoder and octal priority encoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-priority-encoder) — Digital Logic, chapter 4, asked 3×
- [Define combinational logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acombinational-circuit-define) — Digital Logic, chapter 3
- [K-map Σ(0,2,3,4,7,8,10,13)+d, logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-logic-circuit-0234) — Digital Logic, chapter 3