---
title: "Priority encoder; 4-to-2 priority encoder logic"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:priority-encoder-4to2-expressions"
source: https://www.bctengineer.com/q/semester_3/digital_logic/priority-encoder-4to2-expressions
site: BCT Engineering
---

# Priority encoder; 4-to-2 priority encoder logic

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2080 Baisakh, 2+4 marks
- Video: [U2 L7.3 | | Priority Encoder | 4 to 2  Priority Encoder | Priority Encoder: Truth Table, K-Map](https://www.youtube.com/watch?v=PKvCCzxew2g) — Techno Tutorials ( e-Learning)
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/priority-encoder-4to2-expressions
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

What is a priority encoder? Find out logic expressions and draw the logic circuit of 4 to 2 priority encoder.

## Short answer

A priority encoder outputs the code of the highest-priority active input with a valid bit V. For 4-to-2 (D3 highest): Y1=D3+D2, Y0=D3+D2' D1, V=D3+D2+D1+D0. Circuit uses OR, AND, NOT gates.

## Answer

A **priority encoder** is an encoder that gives the binary code of the **highest-priority** active input when more than one input is active at the same time. It also has a valid output $V$ that shows whether any input is active (an ordinary encoder gives a wrong code when two inputs are high).

#### 4-to-2 priority encoder

Inputs $D_0$–$D_3$, with $D_3$ the highest priority. Outputs $Y_1Y_0$ and $V$ (X = don't care).

| $D_3$ | $D_2$ | $D_1$ | $D_0$ | $Y_1$ | $Y_0$ | $V$ |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | X | X | 0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | X | 0 | 1 | 1 |
| 0 | 1 | X | X | 1 | 0 | 1 |
| 1 | X | X | X | 1 | 1 | 1 |

**Expressions** (from K-maps of the expanded table):

- $Y_1 = 1$ when $D_3 = 1$ or $D_2 = 1$:
$$
Y_1 = D_3 + D_2
$$
- $Y_0 = 1$ when $D_3 = 1$, or when $D_1 = 1$ with $D_2 = 0$ (and $D_3=0$):
$$
Y_0 = D_3 + D_3'D_2'D_1 = D_3 + D_2'D_1
$$
- $V$ is 1 if any input is 1:
$$
V = D_3 + D_2 + D_1 + D_0
$$

**Logic circuit**

```text
D3 -----------+---------> [OR] --> Y1
D2 ---+-------|---------> [  ]
      |       |
      +-[NOT]-|-+
              | [AND]-+
D1 -----------|-[   ] +-> [OR] --> Y0
              +---------> [  ]

D0,D1,D2,D3 ----------> [4-in OR] --> V
```

So the circuit needs one NOT, one 2-input AND, two 2-input OR gates and one 4-input OR gate. Example: $D_3D_2D_1D_0 = 0110$ gives $Y_1Y_0 = 10$ because $D_2$ has higher priority than $D_1$.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does a priority encoder do when several inputs are active?
   A. Outputs the code of the lowest input
   B. Outputs 000
   C. Ignores all inputs
   D. Outputs the code of the highest-priority active input
   Answer: D. An ordinary encoder gives a wrong code in that case. (Key point: Priority encoder)

2. What is Y1 for the 4-to-2 priority encoder?
   A. D3 + D2
   B. D3 + D1
   C. D2 + D1
   D. D1 + D0
   Answer: A. Codes 10 and 11 (from D2 and D3) have Y1 = 1. (Key point: Y1)

3. What is Y0?
   A. D3 + D1
   B. D3 + D2'D1
   C. D3 + D2
   D. D1 + D0
   Answer: B. D1 produces Y0 = 1 only if D2 and D3 are not active. (Key point: Y0)

4. What does the V output indicate?
   A. Which input has highest priority
   B. Number of active inputs
   C. At least one input is active, V = D3+D2+D1+D0
   D. An error in the circuit
   Answer: C. V distinguishes all-zero inputs from D0 active. (Key point: Valid output)

## Related in Digital Logic

- [Priority encoder; "e" and "f" segments](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-e-f-segments) — Digital Logic, chapter 4
- [4:2 priority encoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apriority-encoder-4to2) — Digital Logic, chapter 4
- [Priority encoder and octal priority encoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-priority-encoder) — Digital Logic, chapter 4, asked 3×
- [Octal priority encoder design](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aoctal-priority-encoder-design) — Digital Logic, chapter 4, asked 3×
- [K-map Σ(0,2,3,4,7,8,10,13)+d, logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-logic-circuit-0234) — Digital Logic, chapter 3
- [Define combinational logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acombinational-circuit-define) — Digital Logic, chapter 3

## Related in other subjects

- [Preemptive priority and SRTF Gantt](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Apreemptive-priority-srtf-gantt) — Operating System, chapter 2