--- title: "Propagation delay; 3-input CMOS NOR" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:propagation-delay-cmos-nor-3input" source: https://www.bctengineer.com/q/semester_3/digital_logic/propagation-delay-cmos-nor-3input site: BCT Engineering --- # Propagation delay; 3-input CMOS NOR Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2081 Bhadra, 2+5 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/propagation-delay-cmos-nor-3input - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Explain propagation delay. Explain briefly the operation of 3-input CMOS NOR gate with its neat circuit diagram. ## Short answer Propagation delay is the time between input and output changes measured at 50% points, with tPHL and tPLH; average tpd = (tPHL+tPLH)/2. A 3-input CMOS NOR gate has three PMOS in series and three NMOS in parallel; output is low if any input is high, high only when all inputs are low. ## Answer #### Propagation delay **Propagation delay** is the time between a change at a gate's input and the resulting change at its output, measured between the 50% points of the input and output edges. - $t_{PHL}$: delay when the output goes from HIGH to LOW. - $t_{PLH}$: delay when the output goes from LOW to HIGH. - Average delay: $t_{pd} = \dfrac{t_{PHL} + t_{PLH}}{2}$. ```text In ____/--------\______ 50% 50% Out -------\________/---- |<->| |<->| tPHL tPLH ``` It limits the maximum operating speed (typical: about 10 ns for 74LS TTL, about 8–10 ns for 74HC CMOS). #### 3-input CMOS NOR gate It uses 3 PMOS transistors **in series** between $V_{DD}$ and the output (pull-up network) and 3 NMOS transistors **in parallel** between the output and ground (pull-down network). Each input A, B, C drives the gates of one PMOS and one NMOS. ```text VDD | A --o| P1 | B --o| P2 | C --o| P3 | +------------- Y = (A+B+C)' | | | A --| N1 B --| N2 C --| N3 | | | GND GND GND ``` **Operation:** - **All inputs 0:** all three PMOS are ON (gate low) and all NMOS are OFF. The series PMOS chain connects Y to $V_{DD}$, so **Y = 1**. - **Any input 1:** that input's NMOS turns ON and pulls Y to ground, and its PMOS turns OFF, breaking the pull-up chain. So **Y = 0**. - In every case only one network conducts, so no steady current flows from $V_{DD}$ to ground: static power is almost zero. | A | B | C | P1 P2 P3 | N1 N2 N3 | Y | |---|---|---|---|---|---| | 0 | 0 | 0 | ON ON ON | OFF OFF OFF | 1 | | 0 | 0 | 1 | ON ON OFF | OFF OFF ON | 0 | | 0 | 1 | 0 | ON OFF ON | OFF ON OFF | 0 | | 0 | 1 | 1 | ON OFF OFF | OFF ON ON | 0 | | 1 | 0 | 0 | OFF ON ON | ON OFF OFF | 0 | | 1 | 0 | 1 | OFF ON OFF | ON OFF ON | 0 | | 1 | 1 | 0 | OFF OFF ON | ON ON OFF | 0 | | 1 | 1 | 1 | OFF OFF OFF | ON ON ON | 0 | Hence $Y = \overline{A + B + C}$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Propagation delay of a gate is measured as the time between which points? A. The 10% and 90% points of the output edge B. The 50% point of the input edge and the 50% point of the output edge C. The moment power is applied and the output becomes stable D. The 0 V level of the input and the VCC level of the output Answer: B. It is the time from the 50% point of the input change to the 50% point of the resulting output change. (Key point: Propagation delay definition) 2. What does tPLH represent? A. The delay when the output goes from HIGH to LOW B. The delay when the input goes from LOW to HIGH, regardless of output C. The delay when the output goes from LOW to HIGH D. The average of rise and fall times Answer: C. tPLH is the output LOW-to-HIGH delay; tPHL is the HIGH-to-LOW delay. (Key point: tPHL and tPLH) 3. How are the transistors arranged in a 3-input CMOS NOR gate? A. 3 PMOS in series (pull-up) and 3 NMOS in parallel (pull-down) B. 3 PMOS in parallel and 3 NMOS in series C. 3 PMOS in series and 3 NMOS in series D. 3 PMOS in parallel and 3 NMOS in parallel Answer: A. NOR needs all PMOS ON to give 1 (series) and any NMOS ON to give 0 (parallel). (Key point: 3-input CMOS NOR structure) 4. In the 3-input CMOS NOR gate, what happens when A = 1 and B = C = 0? A. All PMOS stay ON so Y = 1 B. Y floats since no path is complete C. Both pull-up and pull-down conduct and Y is half VDD D. N1 turns ON and pulls Y to ground while P1 breaks the pull-up chain, so Y = 0 Answer: D. A single HIGH input turns ON its NMOS to ground and turns OFF its PMOS, which opens the series pull-up path. (Key point: NOR operation) 5. Why does the CMOS NOR gate have almost zero static power? A. Its transistors have no gate capacitance B. Only one of the pull-up and pull-down networks conducts in steady state, so no DC path from VDD to ground C. It operates at a very low voltage D. Both networks conduct but with high resistance Answer: B. The networks are complementary, so there is never a steady current path from VDD to ground. (Key point: Static power) ## Related in Digital Logic - [TTL NOR gate; propagation delay](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-propagation-delay) — Digital Logic, chapter 10 - [CMOS characteristics; 2-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-characteristics-nor-2input) — Digital Logic, chapter 10 - [TTL OR gate; propagation delay and power](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-or-propagation-power) — Digital Logic, chapter 10 - [3-input CMOS gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-three-input-gate) — Digital Logic, chapter 10 - [Propagation delay; 2-input TTL NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-ttl-nand) — Digital Logic, chapter 10 - [TTL NOR gate; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-cmos-characteristics) — Digital Logic, chapter 10 ## Related in other subjects - [CMOS inverter / NOT gate operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-inverter-operation) — Basic Electronics Engineering, chapter 3, asked 4× - [CMOS NAND, NOR (and NOT) circuits](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acmos-nand-nor-circuits) — Embedded System, chapter 8, asked 2× - [Short note: Ex-OR and Ex-NOR gate](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-xor-xnor) — Basic Electrical and Electronics Engineering, chapter 3 - [CMOS switch operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-switch) — Basic Electronics Engineering, chapter 3