--- title: "Propagation delay; 2-input TTL NAND" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:propagation-delay-ttl-nand" source: https://www.bctengineer.com/q/semester_3/digital_logic/propagation-delay-ttl-nand site: BCT Engineering --- # Propagation delay; 2-input TTL NAND Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2080 Bhadra, 2+6 marks - Video: [Transistor Transistor Logic (TTL): TTL NAND Gate Circuit and Working](https://www.youtube.com/watch?v=6Zd582d-PfU) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/propagation-delay-ttl-nand - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Define the propagation delay time. Draw the schematic diagram of a 2-input TTL NAND gate and explain its logic operation. ## Short answer Propagation delay is the time from 50% of input edge to 50% of output edge; tPHL and tPLH average to tpd ~9 ns for 7400 TTL. A 2-input TTL NAND uses a multi-emitter input transistor: any input low turns off Q2/Q4, output high; all inputs high saturate Q2/Q4, output low. ## Answer #### Propagation delay time **Propagation delay** is the time a gate's output takes to respond to a change at its input, measured from the 50% point of the input edge to the 50% point of the output edge. - $t_{PHL}$: input change to output going HIGH → LOW. - $t_{PLH}$: input change to output going LOW → HIGH. - Average: $t_{pd} = \dfrac{t_{PHL} + t_{PLH}}{2}$. For standard 7400 TTL, $t_{PLH} \approx 11$ ns and $t_{PHL} \approx 7$ ns, so $t_{pd} \approx 9$ ns. ```text In ____/--------\_______ : : Out -----:-\_______:-/---- |<>| |<>| tPHL tPLH ``` Smaller delay means a faster gate (higher maximum frequency). #### 2-input TTL NAND gate A **TTL NAND gate** (7400) is built with bipolar transistors: a multi-emitter input transistor, a phase splitter and a totem-pole output. ```text +5 V +-----------+----------+ | | | R1 4k R2 1.6k R4 130 | | | b +-----+ c A--e Q1 | +--b Q3 B--e c--+ c e +--b Q2 | e D1 | | +-----+ +---- Y | | c R3 1k +--b Q4 | e GND --------+----------+ ``` (b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.) **Circuit parts (standard 7400):** - **Q1 (multi-emitter input transistor):** one emitter per input; works like an AND of diodes. - **Q2 (phase splitter):** gives opposite signals at its collector and emitter to drive the output pair. - **Q3, D1, Q4 (totem-pole output):** Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching. **Operation:** - **Any input LOW (≈ 0.2 V):** that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to turn on the Q1 base–collector junction plus Q2 and Q4 (needs about 1.4 V), so **Q2 and Q4 are OFF**. Q2's collector is pulled up through R2, so **Q3 conducts** as an emitter follower and the output is HIGH (about 3.4 V with no load, at least 2.4 V guaranteed). - **All inputs HIGH:** all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2, so **Q2 and Q4 saturate**. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so **Q3 is OFF**. | A | B | Q2, Q4 | Q3 | Y | |---|---|---|---|---| | 0 | 0 | OFF | ON | 1 | | 0 | 1 | OFF | ON | 1 | | 1 | 0 | OFF | ON | 1 | | 1 | 1 | ON | OFF | 0 | Hence $Y = \overline{AB}$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Propagation delay of a gate is measured as the time between which points? A. The 10% and 90% points of the output edge B. The moment power is applied and the output becomes stable C. The 50% point of the input edge and the 50% point of the output edge D. The 0 V level of the input and the VCC level of the output Answer: C. It is the time from the 50% point of the input change to the 50% point of the resulting output change. (Key point: Propagation delay definition) 2. For a standard 7400 TTL gate with tPLH about 11 ns and tPHL about 7 ns, what is t_pd? A. About 18 ns B. About 9 ns C. About 4 ns D. About 11 ns Answer: B. (11 + 7)/2 = 9 ns. (Key point: tPHL and tPLH) 3. What is the role of Q1 in the TTL NAND gate? A. Multi-emitter input transistor with one emitter per input, acting like an AND of diodes B. Phase splitter driving the totem pole C. Active pull-up output transistor D. Clamping diode to keep Q3 off Answer: A. Q1 provides the AND-like input function; Q2 is the phase splitter and Q3/Q4 the output. (Key point: Multi-emitter input) 4. When any input of the TTL NAND is LOW, what happens? A. Q2 and Q4 saturate and Y is LOW B. Q1 base-collector junction conducts into Q2 so Y is LOW C. All transistors are OFF and Y is Hi-Z D. Q1 base is held near 0.9 V so Q2 and Q4 are OFF, Q3 is ON and Y is HIGH Answer: D. A conducting emitter junction clamps Q1's base at about 0.9 V, too low to turn on Q2 and Q4, so Q3 pulls the output HIGH. (Key point: Any input low) 5. When all inputs are HIGH, why is Q3 OFF? A. R4 disconnects Q3 from VCC B. Q1 emitters conduct heavily C. Q2 collector is only about 0.9 V, too low to forward bias Q3's base-emitter and D1 D. Q4 is OFF Answer: C. With Q2 saturated its collector sits near 0.9 V; Q3 and D1 together need about 1.4 V, so Q3 is OFF and Y is LOW. (Key point: All inputs high) ## Related in Digital Logic - [TTL OR gate; propagation delay and power](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-or-propagation-power) — Digital Logic, chapter 10 - [TTL NOR gate; propagation delay](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-propagation-delay) — Digital Logic, chapter 10 - [2-input TTL NAND gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-2input) — Digital Logic, chapter 10 - [2-input TTL NAND; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-cmos-characteristics) — Digital Logic, chapter 10 - [TTL NAND gate; transistor switch](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-transistor-switch) — Digital Logic, chapter 10 - [3-input TTL NAND; totem-pole output](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-3input-totem-pole) — Digital Logic, chapter 10 ## Related in other subjects - [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6