--- title: "Race around condition; JK to SR conversion" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:race-around-jk-to-sr" source: https://www.bctengineer.com/q/semester_3/digital_logic/race-around-jk-to-sr site: BCT Engineering --- # Race around condition; JK to SR conversion Digital Logic · Chapter 6: Flip Flops - Asked in: 2078 Kartik, 2+2+4 marks - Video: [Race Around Condition or Racing in JK Flip Flop](https://www.youtube.com/watch?v=trPGhO7MPnw) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/race-around-jk-to-sr - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Define race around condition. What are the limitation of SR flip flop? Convert JK flip flop to SR flip flop. ## Short answer Race-around is repeated toggling in a level-triggered JK flip-flop with J=K=1 when clock pulse width exceeds propagation delay. SR flip-flop limitations: S=R=1 is forbidden and can cause an indeterminate output state. To convert JK to SR, connect J=S and K=R directly—no extra gates needed. ## Answer #### Race-around condition In a **level-triggered** J-K flip-flop with J = K = 1, the output toggles once after one propagation delay $\Delta t$. If the clock is still high, the new output feeds back to the input gates and makes it toggle again, and again, as long as CLK = 1. At the end of the pulse the output state is unpredictable. This repeated toggling during one clock pulse is the **race-around condition**. It happens when the clock pulse width $t_p > \Delta t$. ```text CLK ___|‾‾‾‾‾‾‾‾‾‾‾‾|___ Q ___|‾‾|__|‾‾|__|‾‾‾ (J = K = 1) ``` It is avoided by keeping $t_p < \Delta t < T$, by edge triggering, or by a master-slave J-K flip-flop. #### Limitations of S-R flip-flop - S = R = 1 is a **forbidden** input: both outputs become equal (not complements). - If S and R go from 1,1 to 0,0 together, the final state is **indeterminate** (depends on gate speeds). - So the circuit using it must always prevent S = R = 1; it cannot toggle and is not directly useful for counters. #### Converting J-K flip-flop to S-R flip-flop J-K excitation table: | Q | Q+ | J | K | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | x | | 1 | 0 | x | 1 | | 1 | 1 | x | 0 | Conversion table (Q+ from the S-R table; S = R = 1 is not allowed, so those rows are don't-cares): | S | R | Q | Q+ | J | K | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | x | | 0 | 0 | 1 | 1 | x | 0 | | 0 | 1 | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | x | 1 | | 1 | 0 | 0 | 1 | 1 | x | | 1 | 0 | 1 | 1 | x | 0 | | 1 | 1 | 0 | x | x | x | | 1 | 1 | 1 | x | x | x | K-maps: ```text K-map for J Q\SR 00 01 11 10 0 0 0 x 1 1 x x x x K-map for K Q\SR 00 01 11 10 0 x x x x 1 0 1 x 0 ``` $$ J = S, \qquad K = R $$ ```text +---------+ S -------| J Q |--- Q CLK -----|> JK | R -------| K Q' |--- Q' +---------+ ``` A J-K flip-flop works as an S-R flip-flop with S connected to J and R connected to K directly; no extra gates are needed. (For S = R = 1 it toggles instead of giving an invalid output, but that input is still not used for S-R operation.) ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What causes the race-around condition in a level-triggered J-K flip-flop? A. J = K = 0 with CLK high B. J = K = 1 with the clock still high after one propagation delay, so it toggles repeatedly C. S = R = 1 D. A missing clock Answer: B. The toggled output feeds back while CLK is high and toggles again and again. (Key point: Race-around cause) 2. Race-around occurs when the pulse width t_p is? A. Less than the propagation delay B. Greater than the propagation delay C. Zero D. Equal to the clock period only Answer: B. It occurs when t_p > delta t. (Key point: Race-around condition) 3. Which of these removes race-around? A. Using a longer clock pulse B. Master-slave or edge triggering C. Setting J = K = 0 D. Removing the clock Answer: B. Edge triggering or a master-slave structure lets the output change only once per clock. (Key point: Remedies) 4. How is a J-K flip-flop used as an S-R flip-flop? A. J = S' and K = R' B. J = S and K = R, directly, with no extra gates C. J = R and K = S D. J = S R and K = S + R Answer: B. The K-maps give J = S and K = R. (Key point: J-K to S-R) ## Related in Digital Logic - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [JK to SR flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-to-sr-conversion) — Digital Logic, chapter 6 - [Flip-flop as state machine; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aflipflop-state-machine-sr-to-jk) — Digital Logic, chapter 6 - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [JK over SR advantages; D flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-over-sr-d-flipflop) — Digital Logic, chapter 6 - [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2× ## Related in other subjects - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9