--- title: "Shift register uses; 4-bit ring counter" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:ring-counter-4bit" source: https://www.bctengineer.com/q/semester_3/digital_logic/ring-counter-4bit site: BCT Engineering --- # Shift register uses; 4-bit ring counter Digital Logic · Chapter 7: Registers - Asked in: 2076 Chaitra, 2+5 marks - Video: [Ring Counter](https://www.youtube.com/watch?v=yOW-JsJL1Ks) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ring-counter-4bit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Define shift registers with its application. Explain the working principle of 4 bit Ring counter with its timing diagram. ## Short answer A shift register stores and shifts binary data; uses include serial conversion, delay, and counters. A 4-bit ring counter circulates a single '1' by feeding QD back to DA, starting from 1000. It cycles 1000 → 0100 → 0010 → 0001 → 1000 (mod-4), providing self-decoded outputs with each line high for one clock period. ## Answer #### Shift register and its applications A **shift register** is a chain of flip-flops with a common clock that stores binary data and shifts it one position left or right at each clock pulse. Applications: - Temporary data storage (buffer registers). - Serial-to-parallel and parallel-to-serial conversion (UART, serial communication). - Time delay of serial data by n clock periods. - Arithmetic: shift left/right to multiply or divide by 2. - Ring counters and Johnson (twisted ring) counters, sequence generators. #### 4-bit ring counter A **ring counter** is a shift register whose last output is connected back to the first input, so a single 1 circulates around the ring. A 4-bit ring counter has 4 states (mod-4, mod-n in general). ```text +-----------------------------------------+ | PRE CLR CLR CLR | | +-----+ +-----+ +-----+ +-----+ | +->|D QA|-->|D QB|-->|D QC|-->|D QD|--+ |> | |> | |> | |> | +-----+ +-----+ +-----+ +-----+ CLK ---^---------^---------^---------^ Start pulse: PRESET A, CLEAR B, C, D -> 1000 ``` **Working principle** 1. A start pulse **presets** FF-A and **clears** FF-B, C, D, so QA QB QC QD = 1000. 2. At each rising clock edge every bit moves one place right and QD goes back to QA ($D_A = Q_D$). 3. The single 1 travels A to B to C to D and back to A, giving the sequence 1000, 0100, 0010, 0001, 1000, ... 4. Exactly one output is high at a time, so no decoder is needed; each output is high for one clock period out of every four. | CLK | QA | QB | QC | QD | |---|---|---|---|---| | 0 | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | | 2 | 0 | 0 | 1 | 0 | | 3 | 0 | 0 | 0 | 1 | | 4 | 1 | 0 | 0 | 0 | **Timing diagram** ```text 1 2 3 4 5 6 7 8 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| QA ‾|___________|‾‾‾|___________|‾‾ QB _|‾‾‾|___________|‾‾‾|__________ QC _____|‾‾‾|___________|‾‾‾|______ QD _________|‾‾‾|___________|‾‾‾|__ ``` The frequency at each output is $f_{CLK}/4$. Ring counters are used as sequence (timing) generators and for controlling steps in sequential operations. The drawback is that n flip-flops give only n states. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is a shift register? A. A chain of flip-flops with a common clock that moves stored data one position per clock pulse B. A chain of gates that adds binary numbers C. A single flip-flop that stores one bit forever D. A decoder that selects one of many outputs Answer: A. A shift register is a series of flip-flops with a common clock that stores data and shifts it one place at each pulse. (Key point: Shift register definition) 2. How is a 4-bit ring counter started so that a single 1 circulates? A. All flip-flops are cleared to 0000 B. All flip-flops are preset to 1111 C. FF-A is preset and FF-B, C, D are cleared, giving 1000 D. FF-D is preset and the others cleared, giving 0001 with D_A = QD' Answer: C. A start pulse presets FF-A and clears the others so QA QB QC QD = 1000. (Key point: Initial condition) 3. In a 4-bit ring counter (D_A = QD), what state follows 0010? A. 0100 B. 0001 C. 1000 D. 0011 Answer: B. The single 1 shifts one place right each clock: 1000, 0100, 0010, 0001. (Key point: Feedback and sequence) 4. Which statement about the 4-bit ring counter is correct? A. It has 8 states and needs a decoder B. Each output has frequency f_CLK/4 and only one output is high at a time, so no decoder is needed C. Each output has frequency f_CLK/2 and all outputs are high together D. It has 4 states but each output is high for 2 of every 4 clocks Answer: B. Each output is high for one clock in four (f_CLK/4); one-hot outputs make it self-decoding. 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