--- title: "Asynchronous (ripple) decade counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:ripple-decade-counter" source: https://www.bctengineer.com/q/semester_3/digital_logic/ripple-decade-counter site: BCT Engineering --- # Asynchronous (ripple) decade counter Digital Logic · Chapter 8: Counters - Asked in: 2075 Chaitra, 5 marks; 2072 Chaitra, 5+2 marks (asked 2 times) - Video: [Decade (BCD) Ripple Counter](https://www.youtube.com/watch?v=fKVZpupyP_o) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/ripple-decade-counter - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Construct an Asynchronous Decade counter. ## Short answer An asynchronous decade counter uses 4 negative-edge JK flip-flops (J=K=1) with the first FF clocked externally, each subsequent FF clocked by the previous Q output. It counts 0000–1001; a NAND gate of Q3 and Q1 drives clear to reset on count 10 (1010), returning to 0000. ## Answer An **asynchronous (ripple) decade counter** is a mod-10 ripple counter: it counts 0000 to 1001 and resets to 0000 on the 10th clock pulse. #### Design - Number of flip-flops: $2^n \ge 10 \Rightarrow n = 4$ JK flip-flops, negative-edge triggered, all with $J = K = 1$ (toggle mode). - The clock drives FF0 only; $Q_0$ clocks FF1, $Q_1$ clocks FF2, $Q_2$ clocks FF3. - The counter must reset when the count reaches 10 = **1010**. In 1010, $Q_3 = 1$ and $Q_1 = 1$; this is the first count in which both are 1. So a 2-input NAND gate of $Q_3$ and $Q_1$ drives the active-low CLEAR inputs of all flip-flops. #### Circuit diagram ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | | NAND |o--> CLR of all FFs (active low) Q1 ---| | ``` #### Count sequence | Clock | Q3 Q2 Q1 Q0 | Decimal | |---|---|---| | 0 | 0 0 0 0 | 0 | | 1 | 0 0 0 1 | 1 | | 2 | 0 0 1 0 | 2 | | 3 | 0 0 1 1 | 3 | | 4 | 0 1 0 0 | 4 | | 5 | 0 1 0 1 | 5 | | 6 | 0 1 1 0 | 6 | | 7 | 0 1 1 1 | 7 | | 8 | 1 0 0 0 | 8 | | 9 | 1 0 0 1 | 9 | | 10 | 1 0 1 0 → 0 0 0 0 | 0 (reset) | #### Operation On each falling clock edge FF0 toggles. Each later flip-flop toggles when the previous output falls from 1 to 0, so the count goes up by one per clock. At the 10th pulse the counter momentarily enters 1010; NAND output goes low and clears all flip-flops to 0000 within a few nanoseconds. The state 1010 lasts only for this short time, so the counter shows 0 to 9. #### Timing diagram ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 8 9 0 ``` (A very short spike on $Q_1$ at the 10th edge, caused by the 1010 state, is ignored in the ideal diagram.) $Q_3$ has a frequency of $f_{clk}/10$, so the circuit is also a divide-by-10 circuit. IC 7490 is a ready-made decade ripple counter. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. At which count is the asynchronous decade counter cleared, and why? A. At 1001, the last used state B. At 1010, the first state with Q3 = Q1 = 1 C. At 1111, the final state D. At 1000, when Q3 first becomes 1 Answer: B. The counter must reset on count 10 (1010), the first count where Q3 and Q1 are both 1. (Key point: Reset state) 2. Which gate is used, and where does its output go? A. AND of Q3, Q1 to the clock of FF0 B. NAND of Q3 and Q1 to the active-low CLEAR of all flip-flops C. NAND of Q3 and Q2 to the clock of FF3 D. OR of Q3 and Q1 to the J inputs Answer: B. NAND(Q3, Q1) goes low at 1010 and clears all flip-flops through their active-low CLEAR inputs. (Key point: Reset gate) 3. How are the flip-flops clocked in this ripple decade counter (negative-edge, J = K = 1)? A. CLK drives FF0 only; Q0 clocks FF1, Q1 clocks FF2, Q2 clocks FF3 B. CLK drives all four flip-flops C. CLK drives FF3; Q3 clocks FF2 D. Each flip-flop is clocked by the NAND output Answer: A. Only FF0 gets the external clock; each later stage is clocked by the previous output, so the change ripples. (Key point: Ripple clocking) ## Related in Digital Logic - [Comb vs seq; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-comb-seq) — Digital Logic, chapter 8, asked 4× - [Synchronous circuits; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-counter-define) — Digital Logic, chapter 8, asked 2× - [Ripple counter; asynchronous mod-11 up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod11-up-counter) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter, positive edge](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-t-positive) — Digital Logic, chapter 8, asked 3× - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [Synchronous decade counter with timing](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asynchronous-decade-counter) — Digital Logic, chapter 8, asked 2×