--- title: "Setup/hold time; RS to D and JK conversion" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:setup-hold-rs-to-d-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/setup-hold-rs-to-d-jk site: BCT Engineering --- # Setup/hold time; RS to D and JK conversion Digital Logic · Chapter 6: Flip Flops - Asked in: 2074 Asoj, 2+6 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/setup-hold-rs-to-d-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question What is the Setup time and hold time of a flip-flop? With the help of excitation table and K-map, convert R-S flip flop into D and J-K flip flops. ## Short answer Setup time is the minimum stable data before the clock edge; hold time is the minimum after. To convert RS to D flip-flop, use S=D and R=not D. For JK, use S=J Q' and R=K Q, derived from excitation tables and K-maps. ## Answer #### Setup time and hold time - **Setup time ($t_s$ or $t_{su}$):** the minimum time for which the data input(s) (D, J-K, S-R) must be stable **before** the active clock edge, so that the flip-flop reads them correctly. - **Hold time ($t_h$):** the minimum time for which the data input(s) must remain stable **after** the active clock edge. ```text CLK _______________|‾‾‾‾‾‾‾‾‾‾ D XXXX|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|XXXX |<-- ts -->|| ^ active edge ``` If either is violated, the output may be wrong or may go into a metastable state. Typical TTL values: $t_s \approx 20$ ns, $t_h \approx 5$ ns. #### Method of conversion 1. Write the characteristic table of the required flip-flop (inputs and $Q_n$ give $Q_{n+1}$). 2. For each row, read the inputs needed on the available (S-R) flip-flop from its excitation table. 3. Simplify the S and R expressions with K-maps and build the input logic. S-R excitation table used: | Q | Q+ | S | R | |---|---|---|---| | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | x | 0 | #### R-S to D flip-flop | D | Q | Q+ | S | R | |---|---|---|---|---| | 0 | 0 | 0 | 0 | x | | 0 | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | x | 0 | ```text K-map for S Q\D 0 1 0 0 1 1 0 x K-map for R Q\D 0 1 0 x 0 1 1 0 ``` $$ S = D, \qquad R = \overline{D} $$ ```text +---------+ D --+------->| S Q |---> Q | CLK->|> SR | +-[NOT]->| R Q' |---> Q' +---------+ ``` Since R is always the complement of S, the forbidden input S = R = 1 can never occur. #### R-S to J-K flip-flop | J | K | Q | Q+ | S | R | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | x | | 0 | 0 | 1 | 1 | x | 0 | | 0 | 1 | 0 | 0 | 0 | x | | 0 | 1 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 1 | x | 0 | | 1 | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | 1 | ```text K-map for S Q\JK 00 01 11 10 0 0 0 1 1 1 x 0 0 x K-map for R Q\JK 00 01 11 10 0 x x 0 0 1 0 1 1 0 ``` $$ S = J\,\overline{Q}, \qquad R = K\,Q $$ ```text +-----+ +---------+ J -------->| | | | Q' ------->| AND |----->| S Q |---> Q +-----+ | | +-----+ CLK->|> SR | K -------->| | | | Q ------->| AND |----->| R Q' |---> Q' +-----+ +---------+ (Q and Q' are fed back from the outputs) ``` Check: for J = K = 1 with Q = 0, S = 1, R = 0 (set); with Q = 1, S = 0, R = 1 (reset), so the output toggles and S = R = 1 never occurs. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which describes setup and hold times correctly? A. Both before the edge B. Setup: after the edge; hold: before C. Both after the edge D. Setup: before the active edge; hold: after the active edge Answer: D. Data must be stable for t_su before and t_h after the edge. (Key point: Setup and hold) 2. What is the conversion method? A. Write the target characteristic table, read the S and R needed from the SR excitation table, and simplify with K-maps B. Connect the outputs to the inputs C. Use only an inverter D. Swap S and R Answer: A. The target flip-flop's behaviour decides S and R for each row. (Key point: Method) 3. What are S and R for the D flip-flop? A. S = D', R = D B. S = D, R = D' C. S = D Q, R = D' Q' D. S = R = D Answer: B. R = D' means S and R are never both 1. (Key point: SR to D) 4. What are S and R for the JK flip-flop? A. S = Qn, R = Qn' B. S = J, R = K' C. S = J Qn', R = K Qn D. S = J Qn, R = K Qn' Answer: C. S = 1 when J = 1 and Q = 0; R = 1 when K = 1 and Q = 1. (Key point: SR to JK) ## Close variants set in other exams - [Setup/hold time; SR to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asetup-hold-sr-to-jk) — Digital Logic, chapter 6, asked 2× ## Related in Digital Logic - [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6 - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [D and T flip-flops; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ad-t-flipflops-t-to-jk) — Digital Logic, chapter 6 - [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2× - [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6 - [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2× ## Related in other subjects - [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2× - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9