--- title: "Setup/hold time; SR to JK conversion" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:setup-hold-sr-to-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/setup-hold-sr-to-jk site: BCT Engineering --- # Setup/hold time; SR to JK conversion Digital Logic · Chapter 6: Flip Flops - Asked in: 2080 Baisakh, 2+6 marks - Video: [Digital Electronics: Setup and Hold time of a Flip Flop](https://www.youtube.com/watch?v=jffA0cDkntQ) — sacademy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/setup-hold-sr-to-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question What is the Setup time and hold time of a flip-flop? With the help of excitation table and K-map, convert SR flip-flop into JK flip-flop. ## Short answer Setup time is the minimum time data must be stable before the active clock edge; hold time is the minimum time after the edge. To convert an SR flip-flop to a JK flip-flop, use excitation tables and K-maps to derive S = J Q_n' and R = K Q_n, then connect these to the SR inputs. ## Answer #### Setup time and hold time - **Setup time ($t_{su}$):** the minimum time the data input (D, J, K, S, R) must be stable **before** the active clock edge so that the flip-flop reads it correctly. - **Hold time ($t_h$):** the minimum time the data input must stay stable **after** the active clock edge. ```text Data ===X======STABLE=======X==== |<-tsu->|<-th->| CLK ______________|‾‾‾‾‾‾‾‾‾‾‾‾ ^ active edge ``` If either is violated the flip-flop may store a wrong value or go metastable. Both are given in the data sheet; for LS-TTL flip-flops they are of the order of tens of ns ($t_{su}$) and a few ns ($t_h$). #### SR flip-flop into JK flip-flop We add a combinational circuit with inputs J, K and $Q_n$ that drives S and R. **SR excitation table** | $Q_n$ | $Q_{n+1}$ | S | R | |---|---|---|---| | 0 | 0 | 0 | X | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | X | 0 | **Conversion table** | J | K | $Q_n$ | $Q_{n+1}$ | S | R | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | X | | 0 | 0 | 1 | 1 | X | 0 | | 0 | 1 | 0 | 0 | 0 | X | | 0 | 1 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 1 | X | 0 | | 1 | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | 1 | **K-maps** ```text S: KQn=00 01 11 10 R: KQn=00 01 11 10 J=0 0 X 0 0 J=0 X 0 1 X J=1 1 X 0 1 J=1 0 0 1 0 ``` $$ S = J\,Q_n', \qquad R = K\,Q_n $$ **Circuit** ```text J --[AND]-- S +--------+--+-- Q Q'--[ ] | SR FF | | | CLK | | K --[AND]-- R | |--|-+-- Q' Q --[ ] +--------+ | | (feedback of Q, Q' to the AND gates) ``` Check: $J = K = 1$, $Q_n = 1$: $S = 0$, $R = 1$, so Q resets (toggle). The two AND gates never make $S = R = 1$, so the invalid state is removed. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is setup time? A. Time the clock stays high B. Delay from clock edge to output change C. Time the data must stay stable after the clock edge D. Minimum time the data input must be stable before the active clock edge Answer: D. Setup time is measured before the active edge; hold time after it. (Key point: Setup time) 2. What is hold time? A. Minimum time the input must remain stable after the active clock edge B. Time Q holds its value C. Minimum time before the edge D. Width of the clock pulse Answer: A. The input must not change for t_h after the edge. (Key point: Hold time) 3. What can happen if setup or hold time is violated? A. Nothing, edge triggering ignores it B. The flip-flop may store a wrong value or go metastable C. Q is always set D. The clock stops Answer: B. Data sheets give both times because violating them can give wrong or metastable output. (Key point: Violation) 4. What are the S and R expressions when the SR flip-flop is converted into JK? A. S = J K, R = J' K' B. S = J, R = K C. S = J Qn', R = K Qn D. S = J Qn, R = K Qn' Answer: C. The K-maps give S = J Qn' and R = K Qn, which never make S = R = 1. (Key point: Conversion) ## Close variants set in other exams - [Setup/hold time; RS to D and JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asetup-hold-rs-to-d-jk) — Digital Logic, chapter 6, asked 2× ## Related in Digital Logic - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [SR flip-flop diagram, excitation table, equation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-diagram-equation) — Digital Logic, chapter 6 - [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6 - [JK to SR flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-to-sr-conversion) — Digital Logic, chapter 6 - [Flip-flop as state machine; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aflipflop-state-machine-sr-to-jk) — Digital Logic, chapter 6 - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× ## Related in other subjects - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9