--- title: "Shift register and 4-bit PISO operation" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:shift-register-piso" source: https://www.bctengineer.com/q/semester_3/digital_logic/shift-register-piso site: BCT Engineering --- # Shift register and 4-bit PISO operation Digital Logic · Chapter 7: Registers - Asked in: 2068 Baisakh, 2+6 marks - Video: [Shift Register (PISO Mode)](https://www.youtube.com/watch?v=7LmBcGiiYwk) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/shift-register-piso - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question What is a shift register? With clear timing diagram, describe the operation of a 4-bit parallel-in serial-out (PISO) shift register. ## Short answer A shift register is a chain of flip-flops that shifts stored bits with each clock. A 4-bit PISO register loads parallel data (e.g., 1011) when SH/LD' is low, then with SH/LD' high shifts bits right; the serial output QD delivers 1, 1, 0, 1 over four clocks, reading the word LSB first. ## Answer #### Shift register A **shift register** is a group of flip-flops connected in a chain, with a common clock, that stores a binary word and moves (shifts) it one bit position to the right or left at each clock pulse. An n-bit shift register has n flip-flops. Depending on how data is entered and taken out, there are SISO, SIPO, PISO, PIPO and bidirectional/universal shift registers. They are used for data storage, serial-parallel conversion, time delay, and ring/Johnson counters. #### 4-bit PISO shift register The PISO register loads 4 bits in parallel in one clock and sends them out serially, one bit per clock. The example data is 1011. #### Circuit ```text PA PB PC PD | | | | +-----+ +-----+ +-----+ +-----+ 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX | +-----+ | +-----+ | +-----+ | +-----+ | | | | | | | +-----+ | +-----+ | +-----+ | +-----+ |D QA|-+ |D QB|-+ |D QC|-+ |D QD|--> |> | |> | |> | |> | Serial +-----+ +-----+ +-----+ +-----+ out MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P SH/LD' and CLK are common to all stages. ``` ```text One stage (e.g. stage B): QA ---------->+-----+ SH/LD' --+--->| AND |--+ | +-----+ | +----+ | +->| OR |--> DB | +-----+ +->| | +NOT>| AND |--+ +----+ PB ---------->+-----+ DB = SH.QA + SH'.PB ``` - **SH/LD' = 0 (load):** the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time. - **SH/LD' = 1 (shift):** the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD. #### Storing and retrieving 1011 Parallel inputs: PA PB PC PD = 1 0 1 1 (PA = MSB, PD = LSB). 1. **Store (clock 1, SH/LD' = 0):** all bits load together: QA QB QC QD = 1011. The LSB (1) is already at the output QD. 2. **Retrieve (clocks 2, 3, 4, SH/LD' = 1):** each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn. 3. Serial output after clocks 1 to 4: **1, 1, 0, 1**, i.e. 1011 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits. | CLK | SH/LD' | QA | QB | QC | QD | Serial out | |---|---|---|---|---|---|---| | 0 (initial) | - | 0 | 0 | 0 | 0 | - | | 1 | Load | 1 | 0 | 1 | 1 | 1 | | 2 | Shift | 0 | 1 | 0 | 1 | 1 | | 3 | Shift | 0 | 0 | 1 | 0 | 0 | | 4 | Shift | 0 | 0 | 0 | 1 | 1 | | 5 | Shift | 0 | 0 | 0 | 0 | 0 | #### Timing diagram ```text 1 2 3 4 5 CLK _|‾|_|‾|_|‾|_|‾|_|‾| SH/LD' ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾| QA _|‾‾‾|______________ QB _____|‾‾‾|__________ QC _|‾‾‾|___|‾‾‾|______ QD _|‾‾‾‾‾‾‾|___|‾‾‾|__ ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is a shift register? A. A single flip-flop that stores one bit B. A combinational circuit that adds bits C. A counter that counts clock pulses without storing data D. Flip-flops in a chain with a common clock that move stored bits one place per clock Answer: D. It stores a binary word and shifts it left or right at each pulse. (Key point: Definition) 2. What does SH/LD' = 1 do in the PISO? A. Shifts data right one place per clock B. Loads the parallel inputs C. Clears the register D. Stops the clock Answer: A. SH/LD' = 1 enables the upper AND gates so each stage takes its left neighbour. (Key point: Mode control) 3. For word 1011, what is the serial output for clocks 1 to 4? A. 1, 0, 1, 1 B. 1, 1, 0, 1 C. 0, 1, 1, 0 D. 1, 1, 1, 0 Answer: B. LSB first. (Key point: Serial output) 4. After clock 3, what are QA QB QC QD? A. 0101 B. 1011 C. 0010 D. 0100 Answer: C. Load gives 1011, clock 2 gives 0101, clock 3 gives 0010. (Key point: Register state) ## Related in Digital Logic - [4-bit PISO shift register working](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-generic-circuit) — Digital Logic, chapter 7, asked 2× - [SISO shift register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asiso-generic-timing) — Digital Logic, chapter 7, asked 9× - [PISO shift register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1011-store-retrieve) — Digital Logic, chapter 7, asked 4× - [SIPO register with timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asipo-generic-timing) — Digital Logic, chapter 7, asked 2× - [4-bit bidirectional shift register](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abidirectional-shift-register) — Digital Logic, chapter 7 - [PISO register with 1101 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1101-data) — Digital Logic, chapter 7, asked 2× ## Related in other subjects - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [Short note: Shift register and counter](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ashort-note-shift-register-counter) — Basic Electronics Engineering, chapter 6 - [Short note: serial and parallel interface](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aserial-parallel-interface) — Microprocessor, chapter 4 - [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3