---
title: "Short note: binary parallel adder"
subject: "Digital Logic"
chapter: 5
key: "semester_3/digital_logic:short-note-binary-parallel-adder"
source: https://www.bctengineer.com/q/semester_3/digital_logic/short-note-binary-parallel-adder
site: BCT Engineering
---

# Short note: binary parallel adder

Digital Logic · Chapter 5: Arithmetic Circuits

- Asked in: 2076 Asoj
- Video: [4 Bit Parallel Adder using Full Adders](https://www.youtube.com/watch?v=NO7Gt8IDSGA) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/short-note-binary-parallel-adder
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5

## Question

Write a short note on binary parallel adder.

## Short answer

A binary parallel adder adds two n-bit numbers using n cascaded full adders with simultaneous inputs. Each stage: Si = Ai⊕Bi⊕Ci, Ci+1 = AiBi + Ci(Ai⊕Bi). ICs like 7483 (4-bit) are cascaded. Limitation is ripple-carry delay, which carry look-ahead overcomes.

## Answer

A **binary parallel adder** is a combinational circuit that adds two n-bit binary numbers with all bits applied at the same time. It is made of $n$ full adders in cascade; the carry output of each full adder goes to the carry input of the next higher stage.

```text
  A3 B3      A2 B2      A1 B1      A0 B0
 +-----+    +-----+    +-----+    +-----+
 | FA3 |<C3-| FA2 |<C2-| FA1 |<C1-| FA0 |<- C0
 +-----+    +-----+    +-----+    +-----+
  |   |        |          |          |
 C4   S3       S2         S1         S0
```

Each stage: $S_i = A_i \oplus B_i \oplus C_i$, $C_{i+1} = A_iB_i + C_i(A_i \oplus B_i)$.

**Operation:** FA0 adds the LSBs with $C_0$ (0 for plain addition); its carry goes to FA1, and so on. The result is $C_4S_3S_2S_1S_0$. Example: $0101 + 0011 = 01000$ (5 + 3 = 8).

**Features and uses:**
- IC 7483/74283 is a 4-bit binary parallel adder; ICs are cascaded ($C_4$ to next $C_0$) for 8, 12, 16 bits.
- With XOR gates on B and $C_0 = 1$ it becomes an adder/subtractor (2's complement).
- Used in multipliers, BCD adders and the ALU.

**Limitation:** carry propagation (ripple) delay; worst-case delay is $n \times$ one-stage carry delay. A carry look-ahead adder overcomes this.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How is an n-bit binary parallel adder built?
   A. From n full adders in cascade, each carry out feeding the next higher carry in
   B. From one full adder used n times with a clock
   C. From n half adders in parallel with no carry links
   D. From n OR gates and one XOR gate
   Answer: A. Each full adder's carry output goes to the carry input of the next higher stage. (Key point: Structure)

2. What is the main limitation of the binary parallel adder?
   A. It cannot add numbers larger than 4 bits
   B. Ripple carry delay: worst case is n times one stage carry delay
   C. It gives wrong sums for odd inputs
   D. It needs a clock signal
   Answer: B. The carry must ripple through every stage, so delay grows with n; a carry look-ahead adder overcomes this. (Key point: Limitation)

3. How can a parallel adder be made to subtract using 2's complement?
   A. Feed C4 back to C0 with C0 = 0
   B. Put AND gates on the A inputs and set C0 = 0
   C. Put XOR gates on the B inputs and set C0 = 1
   D. Remove the carry links
   Answer: C. XOR gates invert B when subtracting (1's complement) and C0 = 1 adds the extra 1 to form the 2's complement. (Key point: Adder/subtractor)

4. What is the output C4S3S2S1S0 for 0101 + 0011 with C0 = 0?
   A. 10000
   B. 00111
   C. 01010
   D. 01000
   Answer: D. 5 + 3 = 8, which is 01000 with carry out C4 = 0. (Key point: Example)

## Related in Digital Logic

- [3-bit multiplier with binary parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abinary-multiplier-3bit) — Digital Logic, chapter 5
- [4-bit multiplier with parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abinary-multiplier-4bit) — Digital Logic, chapter 5
- [Two 4-bit parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparallel-adder-4bit) — Digital Logic, chapter 5
- [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5

## Related in other subjects

- [Two-tape TM as binary adder](https://www.bctengineer.com/question.md?key=semester_3%2Ftheory_of_computation%3Atm-two-tape-binary-adder) — Theory of Computation, chapter 4